TY - GEN
T1 - Wideband noise cancelling balun LNA with feedback biasing
AU - Fernandes, Miguel D.
AU - Oliveira, Luis B.
AU - Goes, Joao
PY - 2016/7/29
Y1 - 2016/7/29
N2 - In this paper we present a balun low noise amplifier (LNA) in which the noise figure (NF) and power consumption are reduced by using a feedback biasing structure. The circuit is based on a conventional wideband balun LNA with noise cancellation. We propose to replace the typical current source of the CG stage by a transistor that establishes a feedback loop in that stage. This adds a degree of freedom which can be used to vary the CG transistor's transconductance, making it different from the typical value of 20 mS. Thus. we can increase the ratio between the gm of the CG and CS stages, which reduces the LNA NF, area, and power consumption, when compared with conventional circuits. Simulation results, with 65 nm CMOS transistors at 1.2 V supply, show that the LNA bandwidth is 3.4 GHz, the voltage gain is 21.8 dB, and the NF is less than 2.5 dB, with IIP3 above -5 dBm. The power dissipation is 4.3 mW. Another design, concerning linearity, has 18.6 dB voltage gain, NF below 2.9 dB and IIP3 above +3 dBm, over a 5 GHz bandwidth, with power consumption of 8.5 mW.
AB - In this paper we present a balun low noise amplifier (LNA) in which the noise figure (NF) and power consumption are reduced by using a feedback biasing structure. The circuit is based on a conventional wideband balun LNA with noise cancellation. We propose to replace the typical current source of the CG stage by a transistor that establishes a feedback loop in that stage. This adds a degree of freedom which can be used to vary the CG transistor's transconductance, making it different from the typical value of 20 mS. Thus. we can increase the ratio between the gm of the CG and CS stages, which reduces the LNA NF, area, and power consumption, when compared with conventional circuits. Simulation results, with 65 nm CMOS transistors at 1.2 V supply, show that the LNA bandwidth is 3.4 GHz, the voltage gain is 21.8 dB, and the NF is less than 2.5 dB, with IIP3 above -5 dBm. The power dissipation is 4.3 mW. Another design, concerning linearity, has 18.6 dB voltage gain, NF below 2.9 dB and IIP3 above +3 dBm, over a 5 GHz bandwidth, with power consumption of 8.5 mW.
KW - LOW-VOLTAGE APPLICATIONS
UR - http://www.scopus.com/inward/record.url?scp=84983388067&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2016.7527226
DO - 10.1109/ISCAS.2016.7527226
M3 - Conference contribution
AN - SCOPUS:84983388067
SN - 978-1-4799-5342-4
T3 - IEEE International Symposium on Circuits and Systems
SP - 285
EP - 288
BT - 2016 IEEE International Symposium on Circuits and Systems (ISCAS 2016)
PB - Institute of Electrical and Electronics Engineers (IEEE)
CY - New York, USA
T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Y2 - 22 May 2016 through 25 May 2016
ER -