Verilog-A Inductor Compact Model for the Efficient Simulation of Class-D VCOs

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This paper presents the use of a Verilog-A compact
model for integrated spiral inductors, for the simulation of ClassD CMOS oscillators. The model takes into consideration the geometric parameters characterising the inductor layout, as well as the technological parameters. The accuracy of the model is checked against simulations with ASITIC simulator and limitations of the model are established. The model is integrated into Cadence environment, offering the designer the possibility to efficiently simulate radio frequency blocks considering the non-idealities of both the inductors and the transistors in nanometric technologies. The particular case for a class-D oscillator is illustrated.
Original languageEnglish
Pages (from-to)114-118
JournalInternational Journal of Microelectronics and Computer Science
Issue number3
Publication statusPublished - Dec 2016


  • Verilog-A
  • RF modeling
  • tapered Inductor
  • Class D Oscillator


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