Verilog-A Compact Model of Integrated Tapered Spiral Inductors

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a Verilog-A compact model for integrated spiral inductors. The implemented model takes into consideration the geometric parameters characterizing the inductor layout, as well as the technological parameters. The accuracy of the model is checked against simulations with ASITIC simulator and limitations of the model are established. The model is integrated into Cadence environment, offering the designer the possibility to obtain the inductor design using the optimization tools. Moreover, simulation of radio frequency blocks such as voltage controlled oscillators, considering the non-
idealities of both the inductor and the transistors in deep-submicron technologies is offered to the designers.
Original languageEnglish
Title of host publicationProceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016
EditorsA. Napieralski
PublisherIEEE
Pages58-61
Number of pages4
ISBN (Print)978-83-63578-08-4
DOIs
Publication statusPublished - 2 Aug 2016
Event23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES) - Lodz, Poland
Duration: 23 Jun 201625 Jun 2016
Conference number: 23rd

Conference

Conference23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)
Abbreviated title(MIXDES)
CountryPoland
CityLodz
Period23/06/1625/06/16

Keywords

  • Verilog-A
  • RF modeling
  • tapered Inductor

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  • Cite this

    Fino, M. H. S. (2016). Verilog-A Compact Model of Integrated Tapered Spiral Inductors. In A. Napieralski (Ed.), Proceedings of the 23rd International Conference Mixed Design of Integrated Circuits and Systems, MIXDES 2016 (pp. 58-61). IEEE. https://doi.org/10.1109/MIXDES.2016.7529700