Progressive scaling of CMOS technology towards nanoscale regime enables the design of highly integrated systems for the wireless communications market. As technology continues to scale, the variability in process parameters may cause significant deviations in device behaviour. The complexity of designing spiral inductors has lead to the development of multi-objective optimization based design methodologies yielding the generation of Pareto-optimal surfaces. However, the variability of the process parameters is usually ignored, yielding the selection of ideally optimal solutions in detriment of quasi-optimal solutions that may prove to be better, should the robustness against process parameter variation be accounted for. We propose the generation of an extended Pareto front containing both optima and quasi-optima solutions. Finally information on the robustness to process parameter variations, is used for electing the best design solutions.The evaluation of the extended set of sub-optima solutions requires methods capable to find the set of local optima, since solutions that are close to each other in the performance index space may be very distant in the design parameter space.
|Title of host publication||Integrated Circuits for Analog Signal Processing|
|Place of Publication||Dordrecht|
|Publication status||Published - 1 Jan 2013|