Transparent Current Mirrors Using a-GIZO TFTs: Simulation with RBF Models and Fabrication

Elvira Maria Correia Fortunato; Pedro Miguel Cândido Barquinha; Rodrigo Ferrão de Paiva Martins

doi:10.1109/UKSim.2014.98

Transparent Current Mirrors Using a-GIZO TFTs: Simulation with RBF Models and Fabrication

Elvira Maria Correia Fortunato, Pedro Miguel Cândido Barquinha, Rodrigo Ferrão de Paiva Martins

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This paper analyzes transparent two-TFT current mirrors using a-GIZO TFTs with different mirroring ratios. In order to achieve a high mirroring ratio, the output TFT in the circuit employed a fingered structure layout to minimize area and overlap capacitance. The analysis of the current mirrors is performed in three phases. In the first, a radial basis function based (RBF) model is developed using measured data from fabricated TFTs on the same chip. Then, in the second phase, the RBF model is implemented in Verilog-A that is used to simulate two-TFT current mirrors with different mirroring ratios. The simulations are carried out using Cadence spectre simulator. In the third phase, simulation results are validated with the measured response from the fabricated circuits.

Original language	Unknown
Title of host publication	IEEE Computer Society
Pages	582-586
DOIs	https://doi.org/10.1109/UKSim.2014.98
Publication status	Published - 1 Jan 2014
Event	UKSIM '14 Proceedings of the 2014 UKSim-AMSS 16th International Conference on Computer Modelling and Simulation - Duration: 1 Jan 2014 → …

Conference

Conference	UKSIM '14 Proceedings of the 2014 UKSim-AMSS 16th International Conference on Computer Modelling and Simulation
Period	1/01/14 → …

Access to Document

10.1109/UKSim.2014.98

Cite this

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title = "Transparent Current Mirrors Using a-GIZO TFTs: Simulation with RBF Models and Fabrication",

abstract = "This paper analyzes transparent two-TFT current mirrors using a-GIZO TFTs with different mirroring ratios. In order to achieve a high mirroring ratio, the output TFT in the circuit employed a fingered structure layout to minimize area and overlap capacitance. The analysis of the current mirrors is performed in three phases. In the first, a radial basis function based (RBF) model is developed using measured data from fabricated TFTs on the same chip. Then, in the second phase, the RBF model is implemented in Verilog-A that is used to simulate two-TFT current mirrors with different mirroring ratios. The simulations are carried out using Cadence spectre simulator. In the third phase, simulation results are validated with the measured response from the fabricated circuits.",

keywords = "amorphous gallium–indium–zinc–oxide thin-film transistor (a-GIZO TFT), neural modeling, Transparent current mirrors",

author = "Fortunato, {Elvira Maria Correia} and Barquinha, {Pedro Miguel C{\^a}ndido} and Martins, {Rodrigo Ferr{\~a}o de Paiva}",

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AU - Fortunato, Elvira Maria Correia

AU - Barquinha, Pedro Miguel Cândido

AU - Martins, Rodrigo Ferrão de Paiva

N1 - Sem PDF

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N2 - This paper analyzes transparent two-TFT current mirrors using a-GIZO TFTs with different mirroring ratios. In order to achieve a high mirroring ratio, the output TFT in the circuit employed a fingered structure layout to minimize area and overlap capacitance. The analysis of the current mirrors is performed in three phases. In the first, a radial basis function based (RBF) model is developed using measured data from fabricated TFTs on the same chip. Then, in the second phase, the RBF model is implemented in Verilog-A that is used to simulate two-TFT current mirrors with different mirroring ratios. The simulations are carried out using Cadence spectre simulator. In the third phase, simulation results are validated with the measured response from the fabricated circuits.

AB - This paper analyzes transparent two-TFT current mirrors using a-GIZO TFTs with different mirroring ratios. In order to achieve a high mirroring ratio, the output TFT in the circuit employed a fingered structure layout to minimize area and overlap capacitance. The analysis of the current mirrors is performed in three phases. In the first, a radial basis function based (RBF) model is developed using measured data from fabricated TFTs on the same chip. Then, in the second phase, the RBF model is implemented in Verilog-A that is used to simulate two-TFT current mirrors with different mirroring ratios. The simulations are carried out using Cadence spectre simulator. In the third phase, simulation results are validated with the measured response from the fabricated circuits.

KW - amorphous gallium–indium–zinc–oxide thin-film transistor (a-GIZO TFT)

KW - neural modeling

KW - Transparent current mirrors

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DO - 10.1109/UKSim.2014.98

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