TY - JOUR
T1 - Threshold voltage extraction techniques adaptable from sub-micron CMOS to large-area oxide TFT technologies
AU - Samanta, Smrutilekha
AU - Tiwari, Bhawna
AU - Bahubalindruni, Pydi Ganga
AU - Barquinha, Pedro
AU - Goes, Joao
N1 - sem pdf conforme despacho.
Portuguese Foundation for Science and Technology (FCT) under Strategic Project, PEST - UID/EEA/00066/2013
PY - 2017/12
Y1 - 2017/12
N2 - This paper proposed simple and accurate threshold voltage (VTH) extraction techniques, which can be directly adaptable to various semiconductor technologies ranging from deep sub-micron complementary metal-oxide-semiconductor to large-area thin-film transistor devices. These techniques are developed using multiple circuits, namely, a dynamic source follower, an inverter with a diode-connected load and a current mirror topology, which allow a direct determination of VTH. As the proposed techniques are experimented with large-area emerging technologies, which have a stable single type (n-type) transistor, all the designs employed in this work are confined to only n-type transistors for a fair comparison. The semiconductor technologies under consideration are standard complementary metal-oxide-semiconductor (65 and 130 nm) and oxide (indium-gallium-zinc-oxide and zinc-tin-oxide) thin-film transistors. In order to validate the accuracy of the proposed techniques, extracted VTH from these methods are compared against the value from linear transfer characteristics. The resulting relative error is within 5%, reinforcing proposed techniques suitability to different semiconductor technologies ranging from deep sub-micron to large-area transistors.
AB - This paper proposed simple and accurate threshold voltage (VTH) extraction techniques, which can be directly adaptable to various semiconductor technologies ranging from deep sub-micron complementary metal-oxide-semiconductor to large-area thin-film transistor devices. These techniques are developed using multiple circuits, namely, a dynamic source follower, an inverter with a diode-connected load and a current mirror topology, which allow a direct determination of VTH. As the proposed techniques are experimented with large-area emerging technologies, which have a stable single type (n-type) transistor, all the designs employed in this work are confined to only n-type transistors for a fair comparison. The semiconductor technologies under consideration are standard complementary metal-oxide-semiconductor (65 and 130 nm) and oxide (indium-gallium-zinc-oxide and zinc-tin-oxide) thin-film transistors. In order to validate the accuracy of the proposed techniques, extracted VTH from these methods are compared against the value from linear transfer characteristics. The resulting relative error is within 5%, reinforcing proposed techniques suitability to different semiconductor technologies ranging from deep sub-micron to large-area transistors.
KW - Dynamic source follower
KW - Large-area electronics
KW - Oxide TFTs
KW - Sub-micron designs
KW - Threshold voltage extraction techniques
UR - http://www.scopus.com/inward/record.url?scp=85017370067&partnerID=8YFLogxK
U2 - 10.1002/cta.2340
DO - 10.1002/cta.2340
M3 - Article
AN - SCOPUS:85017370067
SN - 0098-9886
JO - International Journal of Circuit Theory and Applications
JF - International Journal of Circuit Theory and Applications
ER -