TY - GEN
T1 - Systematic Design Methodology for Optimization of Voltage Comparators in CMOS Technology
AU - Xavier, João
AU - Barquinha, Pedro
AU - Goes, João
N1 - Funding Information:
info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F00066%2F2020/PT#
info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDP%2F00066%2F2020/PT#
Publisher Copyright:
© 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.
PY - 2023
Y1 - 2023
N2 - The increasing rate of digitalization and the growing use of the Internet-of-Things translate into a rise in demand for sensor-to-digital interface circuits and electronics for processing information. This demand increases the need for a standard workflow, which allows a straightforward comparison between active building-blocks (both amplifiers and comparators) with different architectures. Although comparators are essential building-blocks in many circuit architectures, there is no standard workflow to simulate and compare different circuit topologies. This paper proposes a systematic design workflow to simulate dynamic voltage comparators. The workflow consists of the “testbenches” and a simulation setup for extracting key parameters of comparator performance, such as static-offset, random-offset, worst-case comparison-time for both hard and soft decisions, power dissipation, and input-referred noise. As an example, this paper implements the methodology in Virtuoso environment and presents results for different dynamic comparators in a 28-nm standard bulk-CMOS technology.
AB - The increasing rate of digitalization and the growing use of the Internet-of-Things translate into a rise in demand for sensor-to-digital interface circuits and electronics for processing information. This demand increases the need for a standard workflow, which allows a straightforward comparison between active building-blocks (both amplifiers and comparators) with different architectures. Although comparators are essential building-blocks in many circuit architectures, there is no standard workflow to simulate and compare different circuit topologies. This paper proposes a systematic design workflow to simulate dynamic voltage comparators. The workflow consists of the “testbenches” and a simulation setup for extracting key parameters of comparator performance, such as static-offset, random-offset, worst-case comparison-time for both hard and soft decisions, power dissipation, and input-referred noise. As an example, this paper implements the methodology in Virtuoso environment and presents results for different dynamic comparators in a 28-nm standard bulk-CMOS technology.
KW - Comparator Testbench
KW - Dynamic Comparators
KW - Simulation Workflow
UR - http://www.scopus.com/inward/record.url?scp=85164969648&partnerID=8YFLogxK
U2 - 10.1007/978-3-031-36007-7_21
DO - 10.1007/978-3-031-36007-7_21
M3 - Conference contribution
AN - SCOPUS:85164969648
SN - 978-3-031-36006-0
T3 - IFIP Advances in Information and Communication Technology
SP - 279
EP - 289
BT - Technological Innovation for Connected Cyber Physical Spaces
A2 - Camarinha-Matos, Luís M.
A2 - Ferrada, Filipa
PB - Springer
CY - Cham
T2 - 14th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2023
Y2 - 5 July 2023 through 7 July 2023
ER -