This paper presents an improved single-stage amplifier biased by voltage-combiners, through the proper usage of current starving. The topology designed and fabricated shows an enhancement of the low-frequency gain; an improvement in the establishing time due to enhanced gain-bandwidth product; and a high improvement of the energy-efficiency. The circuit was optimized using AIDA-C, a state-of-the-art multi-objective multi-constraint analog IC sizing and optimization tool, and simulation results demonstrate that a gain above 60 dB and a figure-of-merit over 900 MHz×pF/mA are acquirable with this circuit, using the UMC 130 nm technology design kit. The circuit was fabricated and experimentally measured, presenting a gain of 58 dB with a figure-of-merit of 1102 MHz×pF/mA, for a 3.3 V supply source.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Accepted/In press - 23 Nov 2017|
- Circuits and systems
- Current Starving
- Energy efficiency
- Gain Enhancement.