Lithographic technology has been one of the main upholders to Moore's law in the semiconductor industry for the last decades. The underlying reason that enabled the evolution in semiconductor industry has been a steady silicon wafer printing cost, while being able to dramatically increase the number of nodes that can be printed per chip. Key developments in lithography such as wavelength decreasing, together with performance increase in lens and imaging technology, should be accounted for almost all the reduction of cost per function in integrated circuits technology. In this work, we will be presenting the simulation of two mitigation techniques for the impact of defects introduced by manufacturing processes. Namely, the lithographic mask limited resolution on the geometry of the representative device. These perturbations are a consequence of the lithographic mask limited resolution on the geometry of the representative device. For this purpose, the Beam Propagation and Finite Differences Time Domain methods will be used to simulate a multimode interference structure based on silicon nitride. The structure will be affected by previously mentioned perturbations and we expect results revealing a strong dependence between mask resolution, and imbalance and power loss. Two strategies will be followed concerning the mitigation of power loss and imbalance introduced by the limited resolution of lithographic mask: - Access waveguides tapering; - Adjustable power splitting ratios through the electro-optic effect. Through both strategies we aim to achieve an improvement on device's performance but, in the latter are expected finer tuning capabilities, being enabled by dynamic compensation of power loss and imbalance when in a closed loop control architecture.