TY - GEN
T1 - Silicon nitride based devices: Lithographic mask roughness mitigation
AU - Lourenço, Paulo
AU - Fantoni, Alessandro
AU - Costa, João
AU - Vieira, Manuela
N1 - Funding Information:
This research has been supported by EU funds through the FEDER European Regional Development Fund and by Portuguese national funds provided by FCT - Funda??o para a Ci?ncia e a Tecnologia through grant SFRH/BD/144833/2019 and projects PTDC/NAN-OPT/31311/2017 and UID/EEA/00066/2019, and by projects IPL/2019/BioPlas_ISEL and IPL/2019/MO-TFT_ISEL.
PY - 2020
Y1 - 2020
N2 - Lithographic technology has been one of the main upholders to Moore's law in the semiconductor industry for the last decades. The underlying reason that enabled the evolution in semiconductor industry has been a steady silicon wafer printing cost, while being able to dramatically increase the number of nodes that can be printed per chip. Key developments in lithography such as wavelength decreasing, together with performance increase in lens and imaging technology, should be accounted for almost all the reduction of cost per function in integrated circuits technology. In this work, we will be presenting the simulation of two mitigation techniques for the impact of defects introduced by manufacturing processes. Namely, the lithographic mask limited resolution on the geometry of the representative device. These perturbations are a consequence of the lithographic mask limited resolution on the geometry of the representative device. For this purpose, the Beam Propagation and Finite Differences Time Domain methods will be used to simulate a multimode interference structure based on silicon nitride. The structure will be affected by previously mentioned perturbations and we expect results revealing a strong dependence between mask resolution, and imbalance and power loss. Two strategies will be followed concerning the mitigation of power loss and imbalance introduced by the limited resolution of lithographic mask: - Access waveguides tapering; - Adjustable power splitting ratios through the electro-optic effect. Through both strategies we aim to achieve an improvement on device's performance but, in the latter are expected finer tuning capabilities, being enabled by dynamic compensation of power loss and imbalance when in a closed loop control architecture.
AB - Lithographic technology has been one of the main upholders to Moore's law in the semiconductor industry for the last decades. The underlying reason that enabled the evolution in semiconductor industry has been a steady silicon wafer printing cost, while being able to dramatically increase the number of nodes that can be printed per chip. Key developments in lithography such as wavelength decreasing, together with performance increase in lens and imaging technology, should be accounted for almost all the reduction of cost per function in integrated circuits technology. In this work, we will be presenting the simulation of two mitigation techniques for the impact of defects introduced by manufacturing processes. Namely, the lithographic mask limited resolution on the geometry of the representative device. These perturbations are a consequence of the lithographic mask limited resolution on the geometry of the representative device. For this purpose, the Beam Propagation and Finite Differences Time Domain methods will be used to simulate a multimode interference structure based on silicon nitride. The structure will be affected by previously mentioned perturbations and we expect results revealing a strong dependence between mask resolution, and imbalance and power loss. Two strategies will be followed concerning the mitigation of power loss and imbalance introduced by the limited resolution of lithographic mask: - Access waveguides tapering; - Adjustable power splitting ratios through the electro-optic effect. Through both strategies we aim to achieve an improvement on device's performance but, in the latter are expected finer tuning capabilities, being enabled by dynamic compensation of power loss and imbalance when in a closed loop control architecture.
KW - 3 dB splitter
KW - Beam Propagation Method
KW - Chemical potential
KW - Finite Differences Time Domain
KW - Graphene
KW - Lithographic mask resolution
KW - Multimode Interference
UR - http://www.scopus.com/inward/record.url?scp=85087092688&partnerID=8YFLogxK
U2 - 10.1117/12.2555564
DO - 10.1117/12.2555564
M3 - Conference contribution
AN - SCOPUS:85087092688
T3 - Proceedings of SPIE - The International Society for Optical Engineering
BT - Integrated Photonics Platforms: Fundamental Research, Manufacturing and Applications
A2 - Baets, Roel G.
A2 - O'Brien, Peter
A2 - Vivien, Laurent
PB - SPIE-International Society for Optical Engineering
T2 - Integrated Photonics Platforms 2020: Fundamental Research, Manufacturing and Applications
Y2 - 6 April 2020 through 10 April 2020
ER -