Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits

O. Bellaaj Kchaou, A. Garbaya, M. Kotti, P. Pereira, M. Fakhfakh, Maria Helena Silva Fino

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


This paper deals with multiobjective analog circuit optimization taking into consideration performance sensitivity vis-a-vis parameters' variations. It mainly considers improving computation time of the inloop optimization approaches by including sensitivity considerations in the Pareto front generation process, not as a constraint, but by involving it within the used metaheuristic evolution process. Different approaches are proposed and compared. NSGA-II metaheuristic is considered. The proposed sensitivity aware approaches are showcased via two analog circuits, namely, a second generation CMOS current conveyor and a CMOS voltage follower. We show that the proposed ideas considerably alleviate the long computation time of the process and improve the quality of the generated front, as well.

Original languageEnglish
Pages (from-to)220-226
Number of pages7
JournalIntegration-The Vlsi Journal
Publication statusPublished - 1 Sep 2016


  • CCII-
  • CMOS
  • Inloop optimization
  • Multiobjective optimisation
  • Pareto front
  • Richardson extrapolation technique
  • Sensitivity analysis
  • VF


Dive into the research topics of 'Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits'. Together they form a unique fingerprint.

Cite this