This paper presents the implementation of a coarse-grained Magnetic RAM based Reconfigurable Array. The Reconfigurable Array architecture is organized as a one-dimensional array of programmable ALU, with the configuration bits stored in magnetic random-access memories. The use of MRAM technology to implement run-time reconfigurable hardware devices is a very promising technological solution because MRAM can provide non-volatility with cell areas and access speeds comparable to those of SRAM, and with lower process complexity than flash memory. This type of coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more able to exploit larger amounts of operation-level parallelism than common fine-grained architectures. By substantially reducing the overhead for configurability, this coarse-grain architecture is also more apt to efficiently exploit run-time reconfiguration and therefore to take advantage of multi-context MRAM-based configuration memories.
|Title of host publication||-|
|Publication status||Published - 1 Jan 2009|
|Event||12th EUROMICRO Conference on Digital System Design - |
Duration: 1 Jan 2009 → …
|Conference||12th EUROMICRO Conference on Digital System Design|
|Period||1/01/09 → …|