Robust linear sampling switch for low-voltage SAR ADCs

Bhawna Tiwari, Pydi Ganga Bahubalindruni, Sujay Deb, João Goes

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost constant and low ON-resistance (RON) over complete input signal range without using wide transistors, charge pumps, or both, at low supply voltages. The proposed switch was designed using standard 65 nm CMOS technology. The post-layout simulations have shown a signal to noise and distortion ratio (SNDR) of 87.81 dB, a spurious-free dynamic range (SFDR) of 90 dB and a total harmonic distortion (THD) of -91.5dB at a sampling frequency and supply voltage of 100 MHz and 0.8 V, respectively. In addition, the switch has shown a maximum variation of 1% in RON over input signal amplitude at different process corners and temperature, which is low compared to other sampling switches reported in the literature.

Original languageEnglish
Pages (from-to)345-353
Number of pages9
JournalAnalog Integrated Circuits and Signal Processing
Issue number2
Publication statusPublished - 1 May 2020


  • Linear on-resistance
  • Low-voltage SAR ADCs
  • Robust sampling switch


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