On design of memory retention LDO regulator

I. M. Filanovsky; L. B. Oliveira; V. V. Ivanov

doi:10.1109/NEWCAS.2016.7604744

On design of memory retention LDO regulator

I. M. Filanovsky, L. B. Oliveira, V. V. Ivanov

DEE - Departamento de Engenharia Electrotécnica e de Computadores

Research output: Contribution to conference › Paper › peer-review

Abstract

The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100-300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage (voltage follower). The cell provides the load controlled bias current in the main loop. The regulator is inherently stable: the translinear cell operates outside the gain loop. Even it is not required in memory retention applications, this LDO regulator can provide a fast load step response. The circuit was designed for 130 nm CMOS technology.

Original language	English
DOIs	https://doi.org/10.1109/NEWCAS.2016.7604744
Publication status	Published - 20 Oct 2016
Event	14th IEEE International NEWCAS Conference, NEWCAS 2016 - Vancouver, Canada Duration: 26 Jun 2016 → 29 Jun 2016

Conference

Conference	14th IEEE International NEWCAS Conference, NEWCAS 2016
Country	Canada
City	Vancouver
Period	26/06/16 → 29/06/16

Keywords

LDO regulator
memory retention LDO regulator
translinear circuit

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10.1109/NEWCAS.2016.7604744Licence: Unspecified

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title = "On design of memory retention LDO regulator",

abstract = "The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100-300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage (voltage follower). The cell provides the load controlled bias current in the main loop. The regulator is inherently stable: the translinear cell operates outside the gain loop. Even it is not required in memory retention applications, this LDO regulator can provide a fast load step response. The circuit was designed for 130 nm CMOS technology.",

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N2 - The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100-300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage (voltage follower). The cell provides the load controlled bias current in the main loop. The regulator is inherently stable: the translinear cell operates outside the gain loop. Even it is not required in memory retention applications, this LDO regulator can provide a fast load step response. The circuit was designed for 130 nm CMOS technology.

AB - The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100-300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage (voltage follower). The cell provides the load controlled bias current in the main loop. The regulator is inherently stable: the translinear cell operates outside the gain loop. Even it is not required in memory retention applications, this LDO regulator can provide a fast load step response. The circuit was designed for 130 nm CMOS technology.

KW - LDO regulator

KW - memory retention LDO regulator

KW - translinear circuit

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T2 - 14th IEEE International NEWCAS Conference, NEWCAS 2016

Y2 - 26 June 2016 through 29 June 2016

ER -

On design of memory retention LDO regulator

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Keywords

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