On design of memory retention LDO regulator

I. M. Filanovsky, L. B. Oliveira, V. V. Ivanov

Research output: Contribution to conferencePaperpeer-review


The paper describes operation and design of a memory retention LDO regulator. The LDO regulator is operating in a very wide range of the output currents (up to 100 uA) with a very small quiescent current (in the range of 100-300 nA). In the proposed circuit this range is achieved using a nonlinear translinear cell added to the the unity gain stage (voltage follower). The cell provides the load controlled bias current in the main loop. The regulator is inherently stable: the translinear cell operates outside the gain loop. Even it is not required in memory retention applications, this LDO regulator can provide a fast load step response. The circuit was designed for 130 nm CMOS technology.

Original languageEnglish
Publication statusPublished - 20 Oct 2016
Event14th IEEE International NEWCAS Conference, NEWCAS 2016 - Vancouver, Canada
Duration: 26 Jun 201629 Jun 2016


Conference14th IEEE International NEWCAS Conference, NEWCAS 2016


  • LDO regulator
  • memory retention LDO regulator
  • translinear circuit


Dive into the research topics of 'On design of memory retention LDO regulator'. Together they form a unique fingerprint.

Cite this