On-chip built-in self-test of video-rate ADCs using a 1.5 v CMOS Gaussian noise generator

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.
Original languageEnglish
Title of host publication-
Pages669-672
Number of pages4
DOIs
Publication statusPublished - 1 Jan 2006
Event2005 IEEE Conference on Electron Devices and Solid-State Circuits -
Duration: 1 Jan 2005 → …

Conference

Conference2005 IEEE Conference on Electron Devices and Solid-State Circuits
Period1/01/05 → …

Keywords

  • Gaussian noise (electronic)
  • Algorithms
  • CMOS integrated circuits
  • Electric potential

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