On-chip built-in self-test of video-rate ADCs using a 1.5 v CMOS Gaussian noise generator

Guiomar Evans; João Carlos da Palma Goes; Nuno Filipe Silva Veríssimo Paulino

doi:10.1109/EDSSC.2005.1635363

On-chip built-in self-test of video-rate ADCs using a 1.5 v CMOS Gaussian noise generator

Guiomar Evans, João Carlos da Palma Goes, Nuno Filipe Silva Veríssimo Paulino

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.

Original language	English
Title of host publication	-
Pages	669-672
Number of pages	4
DOIs	https://doi.org/10.1109/EDSSC.2005.1635363
Publication status	Published - 1 Jan 2006
Event	2005 IEEE Conference on Electron Devices and Solid-State Circuits - Duration: 1 Jan 2005 → …

Conference

Conference	2005 IEEE Conference on Electron Devices and Solid-State Circuits
Period	1/01/05 → …

Keywords

Gaussian noise (electronic)
Algorithms
CMOS integrated circuits
Electric potential

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10.1109/EDSSC.2005.1635363

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Cite this

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title = "On-chip built-in self-test of video-rate ADCs using a 1.5 v CMOS Gaussian noise generator",

abstract = "A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.",

keywords = "Gaussian noise (electronic), Algorithms, CMOS integrated circuits, Electric potential",

author = "Guiomar Evans and Goes, {Jo{\~a}o Carlos da Palma} and Paulino, {Nuno Filipe Silva Ver{\'i}ssimo}",

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doi = "10.1109/EDSSC.2005.1635363",

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AU - Goes, João Carlos da Palma

AU - Paulino, Nuno Filipe Silva Veríssimo

PY - 2006/1/1

Y1 - 2006/1/1

N2 - A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.

AB - A new method to perform built-in self-testing of the linearity and noise of ADCs is proposed. The technique uses an integrated CMOS Gaussian noise source as input stimulus together with a simple algorithm based in pre-calculated ROM tables for the DNL/INL measurements. The measured results of the integrated low-voltage noise generator are described. The evaluation of the proposed algorithm is demonstrated through a commercial 10-bit, 4OMS/s ADC and compared with the conventional histogram method using sine waves as input signal. The simplicity of the noise generator and of the digital circuitry together with other advantages pointed-out, clearly demonstrate the attractiveness of the proposed technique.

KW - Gaussian noise (electronic)

KW - Algorithms

KW - CMOS integrated circuits

KW - Electric potential

U2 - 10.1109/EDSSC.2005.1635363

DO - 10.1109/EDSSC.2005.1635363

M3 - Conference contribution

SP - 669

EP - 672

BT - -

T2 - 2005 IEEE Conference on Electron Devices and Solid-State Circuits

Y2 - 1 January 2005

ER -

On-chip built-in self-test of video-rate ADCs using a 1.5 v CMOS Gaussian noise generator

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Keywords

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