Novel linear analog-adder using a-IGZO TFTs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.

Original languageEnglish
Title of host publication2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
PublisherIEEE
Pages2098-2101
Number of pages4
ISBN (Electronic)978-1-4799-5341-7
ISBN (Print)978-1-4799-5342-4
DOIs
Publication statusPublished - 29 Jul 2016
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: 22 May 201625 May 2016

Publication series

NameIEEE International Symposium on Circuits and Systems
PublisherIEEE
Volume2016-July
ISSN (Print)0271-4310
ISSN (Electronic)2379-447X

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period22/05/1625/05/16

Keywords

  • Analog adder
  • IGZO TFTs
  • linearization

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  • Cite this

    Bahubalindruni, P. G., Tavares, V. G., Fortunato, E., Martins, R., & Barquinha, P. (2016). Novel linear analog-adder using a-IGZO TFTs. In 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 (pp. 2098-2101). [7538993] (IEEE International Symposium on Circuits and Systems; Vol. 2016-July). IEEE. https://doi.org/10.1109/ISCAS.2016.7538993