TY - GEN
T1 - Novel linear analog-adder using a-IGZO TFTs
AU - Bahubalindruni, Pydi Ganga
AU - Tavares, Vitor Grade
AU - Fortunato, Elvira
AU - Martins, Rodrigo
AU - Barquinha, Pedro
N1 - The first author would like to thank Prof. Joao Goes for his valuable suggestions. This work is funded by FEDER funds through the COMPETE 2020 Programme and National Funds through FCT - Portuguese Foundation for Science and Technology under the Project Nos. UID/CTM/50025/2013 and EXCL/CTM-NAN/0201/2012. The work has also received funding from the European Communities 7th Framework Programme under grant agreement ICT-2013-10-611070 (i-FLEXIS project) and from H2020 program under ICT-03-2014-644631 (ROLL-OUT project).
PY - 2016/7/29
Y1 - 2016/7/29
N2 - A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.
AB - A novel linear analog adder is proposed only with n-type enhancement IGZO TFTs that computes summation of four voltage signals. However, this design can be easily extended to perform summation of higher number of signals, just by adding a single TFT for each additional signal in the input block. The circuit needs few number of transistors, only a single power supply irrespective of the number of voltage signals to be added, and offers good accuracy over a reasonable range of input values. The circuit was fabricated on glass substrate with the annealing temperature not exceeding 200° C. The circuit performance is characterized from measurements under normal ambient at room temperature, with a power supply voltage of 12 V and a load of ≈ 4 pF. The designed circuit has shown a linearity error of 2.3% (until input signal peak to peak value is 2 V), a power consumption of 78 μW and a bandwidth of ≈ 115 kHz, under the worst case condition (when it is adding four signals with the same frequency). In this test setup, it has been noticed that the second harmonic is 32 dB below the fundamental frequency component. This circuit could offer an economic alternative to the conventional approaches, being an important contribution to increase the functionality of large area flexible electronics.
KW - Analog adder
KW - IGZO TFTs
KW - linearization
UR - http://www.scopus.com/inward/record.url?scp=84983450915&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2016.7538993
DO - 10.1109/ISCAS.2016.7538993
M3 - Conference contribution
AN - SCOPUS:84983450915
SN - 978-1-4799-5342-4
T3 - IEEE International Symposium on Circuits and Systems
SP - 2098
EP - 2101
BT - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
Y2 - 22 May 2016 through 25 May 2016
ER -