Low-power CMOS comparator with embedded amplification for ultra-high-speed ADCs

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7 Citations (Scopus)

Abstract

In this paper the challenge of improving the energy-efficiency of comparators is addressed, by proposing a novel comparator structure, to be used in ultra-high-speed ADCs. In this comparator, the pre-amplification is embedded in the input switched-capacitor network by using the passive-amplification capability of MOS devices. Simulated results show that this comparator exhibits low-offset ultra-fast regeneration-time and high energy-efficiency.

Original languageEnglish
Article number4253460
Pages (from-to)3602-3605
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 27 Sep 2007
Event2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, United States
Duration: 27 May 200730 May 2007

Keywords

  • Energy efficiency
  • Switching networks
  • Amplification
  • Analog to digital conversion
  • CMOS integrated circuits
  • Computer simulation
  • Embedded systems

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