A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs open-loop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.
|Number of pages||4|
|Journal||Proceedings of 2008 Ieee International Symposium on Circuits and Systems, Vols 1-10|
|Publication status||Published - 1 Jan 2008|
- Technical presentations
- Amplifiers (electronic)
- Circuit theory
- Multicarrier modulation