Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback

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3 Citations (Scopus)

Abstract

A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs open-loop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end Sample-and-Hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.
Original languageEnglish
Pages (from-to)2258-2261
Number of pages4
JournalProceedings of 2008 Ieee International Symposium on Circuits and Systems, Vols 1-10
Volume1-10
Issue numberNA
DOIs
Publication statusPublished - 1 Jan 2008

Keywords

  • Pipelines
  • Technical presentations
  • Amplifiers (electronic)
  • Circuit theory
  • Linearization
  • Multicarrier modulation

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