Over the last decades, the lithographic technology has greatly contributed for the confirmation of Moore's law in the semiconductor industry. Key developments in lithography such as the operational wavelength decreasing, together with a performance increase in lens and imaging technology, enabled the reduction of cost per function in integrated circuits technology. In this work, the impact of lithographic defects introduced by the manufacturing process is analyzed through simulations and two mitigation techniques are presented. These perturbations are a consequence of the limited lithographic mask resolution reflected on deviations from the geometry of the ideal device. For this purpose, the Beam Propagation and Finite Differences Time Domain methods have been used to simulate a multi-mode interference structure based on silicon nitride. The structure is affected by random perturbations and the obtained results revealed a strong dependence between mask resolution, and imbalance and power loss. Two strategies have been followed concerning the mitigation of power loss and imbalance: - Access waveguides tapering and adjustable power splitting ratios through the electro-optic effect. Both strategies revealed results that indicate an improvement on device’s performance. However, once built, the former is a static design that favors indiscriminately all propagating modes in the multimode section. In the latter, finer tuning capabilities targeting different propagating modes may be enabled by dynamic compensation of power loss and imbalance, when in a closed loop control architecture. Such a control architecture may operate by sampling the output waveguides, extracting the error signal and, finally, negatively feeding it back to the electro-optic effect system, hence improving imbalance and power loss.
- Beam propagation method
- chemical potential
- finite differences time domain
- lithographic resolution
- multimode interference