Is There a ZTC Biasing Point in the Leading-Edge FET Intrinsic Gain g_mr_DS?

Using a Design-Oriented 5 DC-Parameter MOSFET model along with simulation results derived from advanced 16 nm technology, we demonstrate that a zero temperature coefficient (ZTC) bias point does not exist in the intrinsic gain of the transistor, represented by gmrDS. Instead, it was found that a ZTC zone is present when the transistor operates in a well- saturated condition. Although some temperature dependence persists within this ZTC zone, it is characterized by a low complementary to absolute temperature (CTAT) behavior, as indicated by an effective temperature coefficient (TCeff) under 100 ppm/°C, i.e., 0.01% per each 1 °C. Furthermore, both theoretical analysis and simulation results reveal that the ZTC zone in both strong and weak inversion does not manifest in triode operation due to the pronounced CTAT behavior of rds, which is not adequately compensated by the proportional to absolute temperature (PTAT) behavior of gm. This research highlights the complexities of temperature dependence in MOSFET operations and introduces significant insights into transistor behavior at the nanoscale.