TY - JOUR
T1 - Insight on the SU-8 resist as passivation layer for transparent Ga2O3-In2O3-ZnO thin-film transistors
AU - Fortunato, Elvira Maria Correia
AU - Barquinha, Pedro Miguel Cândido
AU - Martins, Rodrigo Ferrão de Paiva
AU - Pereira, Luis Miguel Nunes
PY - 2010/1/1
Y1 - 2010/1/1
N2 - A nonvacuum and low temperature process for passivating transparent metal oxides based thin-film transistors is presented. This process uses the epoxy-based SU-8 resist which prevents device degradation against environmental conditions, vacuum or sputtering surface damage. The incorporation of SU-8 as a passivation layer is based on the ability of this polymer to provide features with high mechanical and chemical stability. With this approach, lithography is performed to pattern the resist over the active area of the device in order to form the passivation layer. The resulting transistors demonstrate very good electrical characteristics, such as mu(FE)= 61 cm(2)/V s, V-ON=-3 V, ON/OFF= 4.4 x 10(9), and S= 0.28 V/dec. Electrical behavior due to the SU-8/metal oxide interface characteristics is also reported on the basis of Fourier transform infrared analysis. In contrast, we demonstrate how sputtering of SiO2 as a passivation layer results in severely degraded devices that cannot be switched-off. In order to obtain proper working devices, it is shown that SU-8 should be hard baked at 200 degrees C for 1 h in order to obtain a highly cross-linked polymer network. The stability of SU-8 passivated devices over the time of storage, under current bias stress and vacuum conditions is also demonstrated.
AB - A nonvacuum and low temperature process for passivating transparent metal oxides based thin-film transistors is presented. This process uses the epoxy-based SU-8 resist which prevents device degradation against environmental conditions, vacuum or sputtering surface damage. The incorporation of SU-8 as a passivation layer is based on the ability of this polymer to provide features with high mechanical and chemical stability. With this approach, lithography is performed to pattern the resist over the active area of the device in order to form the passivation layer. The resulting transistors demonstrate very good electrical characteristics, such as mu(FE)= 61 cm(2)/V s, V-ON=-3 V, ON/OFF= 4.4 x 10(9), and S= 0.28 V/dec. Electrical behavior due to the SU-8/metal oxide interface characteristics is also reported on the basis of Fourier transform infrared analysis. In contrast, we demonstrate how sputtering of SiO2 as a passivation layer results in severely degraded devices that cannot be switched-off. In order to obtain proper working devices, it is shown that SU-8 should be hard baked at 200 degrees C for 1 h in order to obtain a highly cross-linked polymer network. The stability of SU-8 passivated devices over the time of storage, under current bias stress and vacuum conditions is also demonstrated.
U2 - 10.1063/1.3477192
DO - 10.1063/1.3477192
M3 - Article
SN - 0021-8979
VL - 108
SP - nr. 064505
JO - Journal of Applied Physics
JF - Journal of Applied Physics
IS - 6
ER -