Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

Luís Filipe dos Santos Gomes; João Carlos da Palma Goes; DEE Group Author

doi:10.1109/ICECS.2009.5410771

Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

Luís Filipe dos Santos Gomes, João Carlos da Palma Goes, DEE Group Author

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

This paper presents an improved clock-phase generator, able to provide two non-overlapping phases, with an accurate phase shift of 180 degrees. The circuit relies on a modified version of the classic NAND-based bi-phase clock generator but uses an equalizing transmission gate together with dedicated self-biased logic. Simulation results over PVT corners show that, when compared with the original bi-phase clock generator, the proposed circuit exhibits a reduction in the spread of the phase-skew error by a factor higher than 2.4 whilst dissipating similar power. Moreover, the proposed circuit does not require any kind of calibration.

Original language	Unknown
Title of host publication	-
Pages	763-766
DOIs	https://doi.org/10.1109/ICECS.2009.5410771
Publication status	Published - 1 Jan 2009
Event	ICECS’2009 - 16th IEEE International Conference on Electronics, Circuits, and Systems - Duration: 1 Jan 2009 → …

Conference

Conference	ICECS’2009 - 16th IEEE International Conference on Electronics, Circuits, and Systems
Period	1/01/09 → …

Access to Document

10.1109/ICECS.2009.5410771

http://oa.uninova.pt/2053/

Cite this

@inproceedings{14b73029b4d445d58dcc5b7edc9cc52f,

title = "Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits",

abstract = "This paper presents an improved clock-phase generator, able to provide two non-overlapping phases, with an accurate phase shift of 180 degrees. The circuit relies on a modified version of the classic NAND-based bi-phase clock generator but uses an equalizing transmission gate together with dedicated self-biased logic. Simulation results over PVT corners show that, when compared with the original bi-phase clock generator, the proposed circuit exhibits a reduction in the spread of the phase-skew error by a factor higher than 2.4 whilst dissipating similar power. Moreover, the proposed circuit does not require any kind of calibration.",

author = "Gomes, {Lu{\'i}s Filipe dos Santos} and Goes, {Jo{\~a}o Carlos da Palma} and {DEE Group Author}",

year = "2009",

month = jan,

day = "1",

doi = "10.1109/ICECS.2009.5410771",

language = "Unknown",

isbn = "978-1-4244-5090-9",

pages = "763--766",

booktitle = "-",

note = "ICECS{\textquoteright}2009 - 16th IEEE International Conference on Electronics, Circuits, and Systems ; Conference date: 01-01-2009",

}

TY - GEN

T1 - Improved clock-phase generator based on self-biased CMOS logic for time-interleaved SC circuits

AU - Gomes, Luís Filipe dos Santos

AU - Goes, João Carlos da Palma

AU - DEE Group Author

PY - 2009/1/1

Y1 - 2009/1/1

N2 - This paper presents an improved clock-phase generator, able to provide two non-overlapping phases, with an accurate phase shift of 180 degrees. The circuit relies on a modified version of the classic NAND-based bi-phase clock generator but uses an equalizing transmission gate together with dedicated self-biased logic. Simulation results over PVT corners show that, when compared with the original bi-phase clock generator, the proposed circuit exhibits a reduction in the spread of the phase-skew error by a factor higher than 2.4 whilst dissipating similar power. Moreover, the proposed circuit does not require any kind of calibration.

AB - This paper presents an improved clock-phase generator, able to provide two non-overlapping phases, with an accurate phase shift of 180 degrees. The circuit relies on a modified version of the classic NAND-based bi-phase clock generator but uses an equalizing transmission gate together with dedicated self-biased logic. Simulation results over PVT corners show that, when compared with the original bi-phase clock generator, the proposed circuit exhibits a reduction in the spread of the phase-skew error by a factor higher than 2.4 whilst dissipating similar power. Moreover, the proposed circuit does not require any kind of calibration.

U2 - 10.1109/ICECS.2009.5410771

DO - 10.1109/ICECS.2009.5410771

M3 - Conference contribution

SN - 978-1-4244-5090-9

SP - 763

EP - 766

BT - -

T2 - ICECS’2009 - 16th IEEE International Conference on Electronics, Circuits, and Systems

Y2 - 1 January 2009

ER -