Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners

Rui Manuel Leitão Santos-tavares; João Pedro Abreu de Oliveira; João Carlos da Palma Goes

Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners

Rui Manuel Leitão Santos-tavares, João Pedro Abreu de Oliveira, João Carlos da Palma Goes

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward technique. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz*pF/mA has been achieved).

Original language	Unknown
Title of host publication	Mixed Design of Integrated Circuits and Systems (MIXDES)
Place of Publication	Gdynia, Poland
Publisher	IEEE
Pages	247 - 250
ISBN (Print)	978-83-63578-00-8
Publication status	Published - 1 Jan 2013
Event	21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - Duration: 1 Jan 2013 → …

Conference

Conference	21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Period	1/01/13 → …

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Cite this

@inproceedings{f0be1dc3cc5b4ef987d03701d9e51ab5,

title = "Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners",

abstract = "This paper presents a design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward technique. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz*pF/mA has been achieved).",

author = "Santos-tavares, {Rui Manuel Leit{\~a}o} and Oliveira, {Jo{\~a}o Pedro Abreu de} and Goes, {Jo{\~a}o Carlos da Palma}",

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year = "2013",

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day = "1",

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isbn = "978-83-63578-00-8",

pages = "247 -- 250",

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Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners. / Santos-tavares, Rui Manuel Leitão ; Oliveira, João Pedro Abreu de ; Goes, João Carlos da Palma.

Mixed Design of Integrated Circuits and Systems (MIXDES). Gdynia, Poland : IEEE, 2013. p. 247 - 250.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners

AU - Santos-tavares, Rui Manuel Leitão

AU - Oliveira, João Pedro Abreu de

AU - Goes, João Carlos da Palma

N1 - Sem pdf

PY - 2013/1/1

Y1 - 2013/1/1

N2 - This paper presents a design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward technique. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz*pF/mA has been achieved).

AB - This paper presents a design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward technique. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz*pF/mA has been achieved).

M3 - Conference contribution

SN - 978-83-63578-00-8

SP - 247

EP - 250

BT - Mixed Design of Integrated Circuits and Systems (MIXDES)

PB - IEEE

CY - Gdynia, Poland

Y2 - 1 January 2013

ER -