This paper presents a design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward technique. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz*pF/mA has been achieved).
|Title of host publication||Mixed Design of Integrated Circuits and Systems (MIXDES)|
|Place of Publication||Gdynia, Poland|
|Pages||247 - 250|
|Publication status||Published - 1 Jan 2013|
|Event||21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) - |
Duration: 1 Jan 2013 → …
|Conference||21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)|
|Period||1/01/13 → …|
Santos-tavares, R. M. L., Oliveira, J. P. A. D., & Goes, J. C. D. P. (2013). Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners. In Mixed Design of Integrated Circuits and Systems (MIXDES) (pp. 247 - 250). IEEE.