Gain Enhancement and Input Parasitic Capacitance Reduction of Single-Stage OTAs by Using Differential Voltage Combiners

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Abstract

This paper presents a design of single-stage amplifiers with enhanced DC gain without the need of using any cascode devices or any positive-feedback or feed-forward technique. Instead, two voltage-combiners are used in replacement of the traditional tail current-source that is normally employed to bias the differential-pair. Simulation results of a properly optimized circuit example, using AIDA-C a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, demonstrate that DC gains above 50 dB can be achieved, together with high energy efficiency (a figure-of-merit of about 1300 MHz*pF/mA has been achieved).
Original languageUnknown
Title of host publicationMixed Design of Integrated Circuits and Systems (MIXDES)
Place of PublicationGdynia, Poland
PublisherIEEE
Pages247 - 250
ISBN (Print)978-83-63578-00-8
Publication statusPublished - 1 Jan 2013
Event21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) -
Duration: 1 Jan 2013 → …

Conference

Conference21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
Period1/01/13 → …

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