Abstract
The paper describes evaluation of the first, second and (with most attention to) third harmonics of the drain current in a MOS transistor operating in moderate inversion. The dependence of this current on the gate-source voltage is approximated using a simplified 'reconciliation' model developed by Y. Tsividis. Then, the drain current components depending exponentially on normalized signal voltage are calculated using modified Bessel functions. This approach indicates that the third harmonic has two 'sweet spots' (zero values) but the location of that one corresponding to moderate inversion changes with the signal amplitude. This change makes impossible application of this point for circuit linearization. The second 'sweet spot' is corresponding practically to the strong inversion, and may be used for this purpose. The results of proposed calculation method are compared with that using the traditional approach, for example, Taylor series expansion of the drain current expression for small signal. The traditional method misses the above described, for moderate inversion, detrimental effect of signal amplitude or even loses completely the presence of these spots.
Original language | English |
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Title of host publication | 2017 IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 755-758 |
Number of pages | 4 |
Volume | 2017-August |
ISBN (Electronic) | 9781509063895 |
DOIs | |
Publication status | Published - 2017 |
Event | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 - Boston, United States Duration: 6 Aug 2017 → 9 Aug 2017 |
Conference
Conference | 60th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2017 |
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Country/Territory | United States |
City | Boston |
Period | 6/08/17 → 9/08/17 |
Keywords
- Distortion harmonics
- Linearization
- Moderate inversion
- MOS transistor model
- Strong inversion