FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model

Mikhail Mudrov; Anatoliy Zyuzev; Konstantin Nesterov; Stanimir Valtchev

doi:10.1109/EEEIC.2017.7977827

FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model

Mikhail Mudrov, Anatoliy Zyuzev, Konstantin Nesterov, Stanimir Valtchev

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Citations (Scopus)

Abstract

The Hardware-in-the-Loop (HiL) systems become nowadays popular. In the same time, the Field Programmable Gate Arrays (FPGAs) allow for creating the HiL with time step 1 μs or less. The FPGA usually executes the numerical operations on Fixed Point variables. That is why during the FPGA-based HiL creation process it is important to select a proper number of bits for the modeled variables. A mathematical model based on the induction motor is selected as a basis for comparative tests between the floating point model and the fixed point model. In consequence, recommendations for the Bit Capacity (the length of the digital word) selection are given, based on the obtained results.

Original language	English
Title of host publication	Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)	978-153863916-0
DOIs	https://doi.org/10.1109/EEEIC.2017.7977827
Publication status	Published - 12 Jul 2017
Event	17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017 - Milan, Italy Duration: 6 Jun 2017 → 9 Jun 2017

Conference

Conference	17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017
Country/Territory	Italy
City	Milan
Period	6/06/17 → 9/06/17

Keywords

FPGA
HiL
HiL accuracy
Induction motor
Real-time simulating

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10.1109/EEEIC.2017.7977827

Cite this

Mudrov, M., Zyuzev, A., Nesterov, K., & Valtchev, S. (2017). FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model. In Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017 Article 7977827 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/EEEIC.2017.7977827

Mudrov, Mikhail ; Zyuzev, Anatoliy ; Nesterov, Konstantin et al. / FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model. Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017. Institute of Electrical and Electronics Engineers (IEEE), 2017.

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abstract = "The Hardware-in-the-Loop (HiL) systems become nowadays popular. In the same time, the Field Programmable Gate Arrays (FPGAs) allow for creating the HiL with time step 1 μs or less. The FPGA usually executes the numerical operations on Fixed Point variables. That is why during the FPGA-based HiL creation process it is important to select a proper number of bits for the modeled variables. A mathematical model based on the induction motor is selected as a basis for comparative tests between the floating point model and the fixed point model. In consequence, recommendations for the Bit Capacity (the length of the digital word) selection are given, based on the obtained results.",

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Mudrov, M, Zyuzev, A, Nesterov, K & Valtchev, S 2017, FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model. in Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017., 7977827, Institute of Electrical and Electronics Engineers (IEEE), 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017, Milan, Italy, 6/06/17. https://doi.org/10.1109/EEEIC.2017.7977827

FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model. / Mudrov, Mikhail; Zyuzev, Anatoliy; Nesterov, Konstantin et al.
Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017. Institute of Electrical and Electronics Engineers (IEEE), 2017. 7977827.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - The Hardware-in-the-Loop (HiL) systems become nowadays popular. In the same time, the Field Programmable Gate Arrays (FPGAs) allow for creating the HiL with time step 1 μs or less. The FPGA usually executes the numerical operations on Fixed Point variables. That is why during the FPGA-based HiL creation process it is important to select a proper number of bits for the modeled variables. A mathematical model based on the induction motor is selected as a basis for comparative tests between the floating point model and the fixed point model. In consequence, recommendations for the Bit Capacity (the length of the digital word) selection are given, based on the obtained results.

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Mudrov M, Zyuzev A, Nesterov K, Valtchev S. FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model. In Conference Proceedings - 2017 17th IEEE International Conference on Environment and Electrical Engineering and 2017 1st IEEE Industrial and Commercial Power Systems Europe, EEEIC / I and CPS Europe 2017. Institute of Electrical and Electronics Engineers (IEEE). 2017. 7977827 doi: 10.1109/EEEIC.2017.7977827

FPGA-based Hardware-in-the-Loop system bits capacity evaluation based on induction motor model

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