TY - JOUR
T1 - Flipped-around multiply-by-two amplifier with unity feedback factor
AU - Goes, João Carlos da Palma
AU - Paulino, Nuno Filipe Silva Veríssimo
AU - DEE Group Author
PY - 2011/1/1
Y1 - 2011/1/1
N2 - This letter describes a multiply-by-two amplifier inherently insensitive to capacitor mismatch with an enhanced feedback factor of approximately unity. The proposed flipped-around structure, which operates in a single clock cycle, is based on the series association of two charged capacitors to achieve an accurate gain of two. Due to the series association of the capacitors, a nearly unity feedback factor is achieved, greatly enhancing the energy efficiency of the circuit. Simulations, in a standard 0.13 mu m 1.2 V CMOS technology, also show a fourfold linearity improvement over the conventional structure.
AB - This letter describes a multiply-by-two amplifier inherently insensitive to capacitor mismatch with an enhanced feedback factor of approximately unity. The proposed flipped-around structure, which operates in a single clock cycle, is based on the series association of two charged capacitors to achieve an accurate gain of two. Due to the series association of the capacitors, a nearly unity feedback factor is achieved, greatly enhancing the energy efficiency of the circuit. Simulations, in a standard 0.13 mu m 1.2 V CMOS technology, also show a fourfold linearity improvement over the conventional structure.
U2 - 10.1007/s10470-011-9642-5
DO - 10.1007/s10470-011-9642-5
M3 - Article
SN - 0925-1030
VL - 68
SP - 133
EP - 138
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
IS - 1
ER -
