A fast-settling two-stage completely self-biased amplifier (op amp) is presented. The op amp uses two amplifying stages and feedforward-regulated cascode transistors to achieve high dc gain, while maintaining a reasonable output swing and high-frequency performance. Exhaustive simulation results over corners demonstrate that, after proper time-domain optimization of the proposed op amp in a 0.13-μm CMOS technology, a very fast settling with accuracy over 12 bits can be achieved, while dissipating very low power.
|Title of host publication||IEEE|
|Publication status||Published - 1 Jan 2010|
|Event||2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) - |
Duration: 1 Jan 2010 → …
|Conference||2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)|
|Period||1/01/10 → …|