The estimation of inter-channel mismatches in time-interleaved analog-to-digital converters (TI-ADCs) is a crucial step towards the compensation of output errors inherent of these converters. In this paper, we investigate a fast, accurate and low-complexity method for estimation of static gain and sample-time mismatches. The proposed technique uses a calibration signal generated on-chip through a sinusoidal oscillator inserted into a phase-locked loop (PLL), similarly as the sampling clock signal is usually generated in these high speed conversion systems. We synchronize these two PLLs to allow efficient frequency domain computations, without resorting to windowing, from which accurate estimations are feasible. We show that the accuracy of the method is not affected by nonidealities in the calibration signal as long as the calibration frequency is carefully selected.
|Title of host publication||International Symposium on Circuits and Systems|
|Publication status||Published - 1 Jan 2012|
|Event||Circuits and Systems (ISCAS), 2012 IEEE International Symposium on - |
Duration: 1 Jan 2012 → …
|Conference||Circuits and Systems (ISCAS), 2012 IEEE International Symposium on|
|Period||1/01/12 → …|
Oliveira, L. A. B. G. D., Goes, J. C. D. P., & DEE Group Author (2012). Fast and accurate estimation of gain and sample-time mismatches in time-interleaved ADCs using on-chip oscillators. In International Symposium on Circuits and Systems (pp. 3154-3157) https://doi.org/10.1109/ISCAS.2012.6271991