Where a-Si:H pin devices are concerned, one of the main obstacles regarding improved performance is device stability, usually attributed to adverse behaviour at various interfaces within the device. Several attempts have been made to overcome this problem, such as the use of blocking layers at the interfaces. Although these have led to some improvements in device performance, most of the problems associated with device stability remain. This is mainly due to the defects at the interfaces, since the blocking layers (silicon alloys with carbon, nitrogen or oxygen) usually have a high density of bulk states, in comparison to intrinsic a-Si:H films. In this paper, we present a method that seems to be capable of improving device stability. It consists of performing a controlled removal of oxide interlayers at the interfaces, by an appropriate etching process. This enables the production of highly smoothed interfaces, and reduces possible cross-contamination of the i-layer from the adjacent doped layers. This amounts to a new design of typical pin devices, in which thin absorber layers are placed at the p/i and i/n interfaces. Their purpose is to trap most of the impurity atoms diffused from the doped layers, after which they are removed by appropriate etching. The fabrication of the absorbers (sacrificial layers), the nature of the etching and the tailoring of the defect profile at the interfaces will be discussed, including the performance exhibited by the resulting devices.
- Amorphous silicon
- Solar cells