This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. The architecture of the programmable delay uses a Delta-Sigma modulator to generate a reference clock with a delay unaffected by component matching. This reference clock has a large jitter noise component that is filtered by delay lock loop (DLL). The programmable delay can produce a delay ranging from 20 ns to 100 ns, because of the large delay variation, it is necessary to use a variable charge pump current in the DDL, in order to guaranty stability for all the desired delay values. The electrical design of the circuit, in a 0.13-um 1.2-V CMOS technology, will be presented, as well as electrical simulations results of the complete system.
|Title of host publication||-|
|Publication status||Published - 1 Jan 2010|
|Event||IEEE International Conference on Mixed Design of Integrated Circuits and Systems - |
Duration: 1 Jan 2010 → …
|Conference||IEEE International Conference on Mixed Design of Integrated Circuits and Systems|
|Period||1/01/10 → …|