Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion

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10 Citations (Scopus)

Abstract

This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADC's. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that, reducing the supply voltage does not necessarily increases the used energy per conversion.

Original languageEnglish
Title of host publication2002 IEEE International Symposium on Circuits and Systems
Subtitle of host publicationProceedings: Volume V of V
Place of PublicationPiscataway
PagesI/921-I/924
Number of pages4
VolumeV
DOIs
Publication statusPublished - 2002
Event2002 IEEE International Symposium on Circuits and Systems: ISCAS 2002 - Phoenix, United States
Duration: 26 May 200229 May 2002

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
ISSN (Print)0271-4310

Conference

Conference2002 IEEE International Symposium on Circuits and Systems
Abbreviated titleISCAS 2002
CountryUnited States
CityPhoenix
Period26/05/0229/05/02

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