Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion

Bruno Vaz; Nuno Paulino; João Goes; R. Costa; Rui Tavares; Adolfo Steiger-Garção

doi:10.1109/ISCAS.2002.1009992

Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion

Bruno Vaz, Nuno Paulino, João Goes, R. Costa, Rui Tavares, Adolfo Steiger-Garção

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Citations (Scopus)

Abstract

This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADC's. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that, reducing the supply voltage does not necessarily increases the used energy per conversion.

Original language	English
Title of host publication	2002 IEEE International Symposium on Circuits and Systems
Subtitle of host publication	Proceedings: Volume V of V
Place of Publication	Piscataway
Pages	I/921-I/924
Number of pages	4
Volume	V
DOIs	https://doi.org/10.1109/ISCAS.2002.1009992
Publication status	Published - 2002
Event	2002 IEEE International Symposium on Circuits and Systems: ISCAS 2002 - Phoenix, United States Duration: 26 May 2002 → 29 May 2002

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	IEEE
ISSN (Print)	0271-4310

Conference

Conference	2002 IEEE International Symposium on Circuits and Systems
Abbreviated title	ISCAS 2002
Country/Territory	United States
City	Phoenix
Period	26/05/02 → 29/05/02

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10.1109/ISCAS.2002.1009992Licence: Unspecified

Cite this

Vaz, B., Paulino, N., Goes, J., Costa, R., Tavares, R., & Steiger-Garção, A. (2002). Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion. In 2002 IEEE International Symposium on Circuits and Systems : Proceedings: Volume V of V (Vol. V, pp. I/921-I/924). (Proceedings - IEEE International Symposium on Circuits and Systems).. https://doi.org/10.1109/ISCAS.2002.1009992

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abstract = "This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADC's. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that, reducing the supply voltage does not necessarily increases the used energy per conversion.",

keywords = "pipelined ADC, Optimization methodology, low-power, genetic algorithms, low-voltage",

author = "Bruno Vaz and Nuno Paulino and Jo{\~a}o Goes and R. Costa and Rui Tavares and Adolfo Steiger-Gar{\c c}{\~a}o",

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Vaz, B, Paulino, N , Goes, J, Costa, R, Tavares, R & Steiger-Garção, A 2002, Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion. in 2002 IEEE International Symposium on Circuits and Systems : Proceedings: Volume V of V. vol. V, Proceedings - IEEE International Symposium on Circuits and Systems, Piscataway, pp. I/921-I/924, 2002 IEEE International Symposium on Circuits and Systems, Phoenix, Arizona, United States, 26/05/02. https://doi.org/10.1109/ISCAS.2002.1009992

Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion. / Vaz, Bruno; Paulino, Nuno ; Goes, João et al.
2002 IEEE International Symposium on Circuits and Systems : Proceedings: Volume V of V. Vol. V Piscataway, 2002. p. I/921-I/924 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Steiger-Garção, Adolfo

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AB - This paper presents an optimization methodology based on genetic algorithms for designing low-voltage low-power pipelined ADC's. It is demonstrated that multi-bit rather than minimum resolution-per-stage architectures are better suited for low-voltage operation and also that, either switched-opamp or clock-boosting techniques can produce equivalent realizations in terms of power efficiency. By carefully tailoring the pipelined architecture with the proposed optimization approach it is clearly demonstrated by means of a 1.5V, 10b, 40 MS/s pipeline ADC design example that, reducing the supply voltage does not necessarily increases the used energy per conversion.

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KW - Optimization methodology

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Vaz B, Paulino N , Goes J, Costa R, Tavares R , Steiger-Garção A. Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion. In 2002 IEEE International Symposium on Circuits and Systems : Proceedings: Volume V of V. Vol. V. Piscataway. 2002. p. I/921-I/924. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2002.1009992

Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion

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