TY - JOUR
T1 - Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies
AU - Goes, João Carlos da Palma
AU - Paulino, Nuno Filipe Silva Veríssimo
AU - DEE Group Author
PY - 2010/1/1
Y1 - 2010/1/1
N2 - This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.
AB - This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.
U2 - 10.1007/s10470-009-9357-z
DO - 10.1007/s10470-009-9357-z
M3 - Article
SN - 0925-1030
SP - 13
EP - 22
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
IS - NA
ER -