Design of a low phase error multiphase clock generator for modern wideband receivers

This paper presents the design of a multiphase clock generator that can be integrated in a current-mode wideband receiver. This block consists of a ring of dynamic transmission-gate flip-flops, which generates 8-phase clocks non-overlapped with 12.5% duty-cycle, from an external input clock at eight times the desired output frequency. The circuit is designed using CMOS 65 nm technology with 1 V supply. Simulation results, for 1 GHz output clock, show that the phase error is 0.045°, considering process and mismatch variations of the circuit, with a power consumption of 10 mW, allowing the receiver to achieve HR3,5 > 60 dB for more than 95% of the Monte Carlo runs.