Design of a low phase error multiphase clock generator for modern wideband receivers

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Abstract

This paper presents the design of a multiphase clock generator that can be integrated in a current-mode wideband receiver. This block consists of a ring of dynamic transmission-gate flip-flops, which generates 8-phase clocks non-overlapped with 12.5% duty-cycle, from an external input clock at eight times the desired output frequency. The circuit is designed using CMOS 65 nm technology with 1 V supply. Simulation results, for 1 GHz output clock, show that the phase error is 0.045°, considering process and mismatch variations of the circuit, with a power consumption of 10 mW, allowing the receiver to achieve HR3,5 > 60 dB for more than 95% of the Monte Carlo runs.

Original languageEnglish
Title of host publication2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509004935
DOIs
Publication statusPublished - 2016
Event12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016 - Lisbon, Portugal
Duration: 27 Jun 201630 Jun 2016

Conference

Conference12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016
CountryPortugal
CityLisbon
Period27/06/1630/06/16

Keywords

  • DEFINED RADIO RECEIVER
  • MIXERS
  • PATH

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  • Cite this

    Fernandes, M. D., Oliveira, L. B., Goes, J., & Oliveira, J. P. (2016). Design of a low phase error multiphase clock generator for modern wideband receivers. In 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016 [7519504] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME.2016.7519504