Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver

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2 Citations (Scopus)

Abstract

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.

Original languageEnglish
Title of host publicationProceedings Of The 2003 IEEE International Symposium On Circuits And systems
Subtitle of host publicationBiomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems
Place of PublicationPiscataway
PublisherIEEE
PagesI133-I136
Number of pages4
Volume5
ISBN (Print)0-7803-7761-3
DOIs
Publication statusPublished - 2003
Event2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
Duration: 25 May 200328 May 2003

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE; 1999
ISSN (Print)0271-4310

Conference

Conference2003 IEEE International Symposium on Circuits and Systems
CountryThailand
CityBangkok
Period25/05/0328/05/03

Keywords

  • Ultra wideband radar
  • Delay lines
  • Jitter
  • Timing
  • Signal resolution
  • Modulation coding
  • Matched filters
  • Noise generators
  • Clocks
  • Noise level

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