Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver

Nuno Paulino; Marco Serrazina; João Goes; A. Steiger-Garção

doi:10.1109/ISCAS.2003.1205518

Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver

Nuno Paulino, Marco Serrazina, João Goes, A. Steiger-Garção

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.

Original language	English
Title of host publication	Proceedings Of The 2003 IEEE International Symposium On Circuits And systems
Subtitle of host publication	Biomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	I133-I136
Number of pages	4
Volume	5
ISBN (Print)	0-7803-7761-3
DOIs	https://doi.org/10.1109/ISCAS.2003.1205518
Publication status	Published - 2003
Event	2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand Duration: 25 May 2003 → 28 May 2003

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	IEEE; 1999
ISSN (Print)	0271-4310

Conference

Conference	2003 IEEE International Symposium on Circuits and Systems
Country/Territory	Thailand
City	Bangkok
Period	25/05/03 → 28/05/03

Keywords

Ultra wideband radar
Delay lines
Jitter
Timing
Signal resolution
Modulation coding
Matched filters
Noise generators
Clocks
Noise level

Access to Document

10.1109/ISCAS.2003.1205518Licence: Unspecified

Cite this

Paulino, N., Serrazina, M., Goes, J., & Steiger-Garção, A. (2003). Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. In Proceedings Of The 2003 IEEE International Symposium On Circuits And systems: Biomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems (Vol. 5, pp. I133-I136). (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISCAS.2003.1205518

Paulino, Nuno ; Serrazina, Marco ; Goes, João et al. / Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. Proceedings Of The 2003 IEEE International Symposium On Circuits And systems: Biomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems. Vol. 5 Piscataway : Institute of Electrical and Electronics Engineers (IEEE), 2003. pp. I133-I136 (Proceedings - IEEE International Symposium on Circuits and Systems).

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abstract = "This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.",

keywords = "Ultra wideband radar, Delay lines, Jitter, Timing, Signal resolution, Modulation coding, Matched filters, Noise generators, Clocks, Noise level",

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Paulino, N , Serrazina, M , Goes, J & Steiger-Garção, A 2003, Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. in Proceedings Of The 2003 IEEE International Symposium On Circuits And systems: Biomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems. vol. 5, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE), Piscataway, pp. I133-I136, 2003 IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, 25/05/03. https://doi.org/10.1109/ISCAS.2003.1205518

Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. / Paulino, Nuno ; Serrazina, Marco ; Goes, João et al.
Proceedings Of The 2003 IEEE International Symposium On Circuits And systems: Biomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems. Vol. 5 Piscataway: Institute of Electrical and Electronics Engineers (IEEE), 2003. p. I133-I136 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Goes, João

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N2 - This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.

AB - This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. Traditional delay lines are realized selecting the delayed signal from a tap in a cascade of delay elements, resulting in a delay resolution limited by the matching errors between the delay elements. The architecture of the programmable delay line presented in this paper uses a ΣΔ modulator to generate a delay unaffected by matching and a delay locked loop to filter the excess jitter noise from the output clock. System level simulations show that it is possible to obtain a resolution of 11 bits corresponding to an average output rms jitter noise of 11.4 ps.

KW - Ultra wideband radar

KW - Delay lines

KW - Jitter

KW - Timing

KW - Signal resolution

KW - Modulation coding

KW - Matched filters

KW - Noise generators

KW - Clocks

KW - Noise level

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Paulino N , Serrazina M , Goes J , Steiger-Garção A. Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver. In Proceedings Of The 2003 IEEE International Symposium On Circuits And systems: Biomedical Circuits & Systems: VLSI Systems & Applications: Neural Networks & Systems. Vol. 5. Piscataway: Institute of Electrical and Electronics Engineers (IEEE). 2003. p. I133-I136. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2003.1205518

Design of a digitally programmable delay-locked-loop for a low-cost ultra wide band radar receiver

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