Design of a 28nm CMOS Self-Biased Ring Oscillator for Intrinsically Robust PVT TRNG

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this paper we present a dynamic entropy generator based on the oscillator jitter, which uses a self-biasing technique to minimize process, voltage, and temperature (PVT) variations. The proposed circuit has the advantage of its intrinsic robustness due to self-biasing design, which eliminates the need of additional calibration steps and simplifies the circuit topology, with a negligible impact in area and power consumption. A frequency deviation below 15 % and a maximum jitter difference of 32 % under PVT variations, is obtained, in a 28 nm CMOS technology circuit prototype. For validation of the proposed circuit technique the IC prototype is compared with a standard ring oscillator and with traditional calibration techniques.
Original languageEnglish
Title of host publicationPRIME 2023
Subtitle of host publication18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings
Place of PublicationMassachusetts
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages225-228
Number of pages4
ISBN (Electronic)979-8-3503-0319-3
ISBN (Print)979-8-3503-0321-6
DOIs
Publication statusPublished - 2023
Event18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023 - Valencia, Spain
Duration: 18 Jun 202321 Jun 2023

Conference

Conference18th International Conference on Ph.D Research in Microelectronics and Electronics, PRIME 2023
Country/TerritorySpain
CityValencia
Period18/06/2321/06/23

Keywords

  • Entropy source
  • PVT variations
  • Ring oscillator
  • Security
  • Self-bias circuit
  • TRNG

Fingerprint

Dive into the research topics of 'Design of a 28nm CMOS Self-Biased Ring Oscillator for Intrinsically Robust PVT TRNG'. Together they form a unique fingerprint.

Cite this