Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting

João Carlos da Palma Goes; Nuno Filipe Silva Veríssimo Paulino; DEE Group Author

Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting

João Carlos da Palma Goes, Nuno Filipe Silva Veríssimo Paulino, DEE Group Author

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a 1.5-bit MDAC circuit to be used in pipeline ADCs which employs a switched-current source to perform the reference shifting of the MDAC (the 1.5-bit digital-to-analog function). In the proposed circuit, the two single-ended reference voltage sources that are traditionally used (VREFP and VREFN), are replaced by a switched-current source. To evaluate and compare the performance of the proposed circuit, two 10-bit 40 MS/s ADCs, one using the traditional switched-capacitor (SC) MDAC and the other using the proposed MDAC, are designed. Simulation results show that the performance of the ADC with the proposed MDAC is enhanced since the power needed for the current sources is smaller than the power supplied by the reference voltage sources. Moreover, the proposed circuit does not require any reference voltage buffer, which can be difficult to design with relatively low power dissipation

Original language	Unknown
Title of host publication	Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)
Pages	216-220
Publication status	Published - 1 Jan 2011
Event	Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 - Duration: 1 Jan 2011 → …

Conference

Conference	Mixed Design of Integrated Circuits and Systems (MIXDES), 2011
Period	1/01/11 → …

Access to Document

http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-80053305005&md5=472e2636d1a1d457e90a15322430ade1

Cite this

Goes, J. C. D. P., Paulino, N. F. S. V., & DEE Group Author (2011). Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting. In Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) (pp. 216-220) http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-80053305005&md5=472e2636d1a1d457e90a15322430ade1

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title = "Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting",

abstract = "This paper presents a 1.5-bit MDAC circuit to be used in pipeline ADCs which employs a switched-current source to perform the reference shifting of the MDAC (the 1.5-bit digital-to-analog function). In the proposed circuit, the two single-ended reference voltage sources that are traditionally used (VREFP and VREFN), are replaced by a switched-current source. To evaluate and compare the performance of the proposed circuit, two 10-bit 40 MS/s ADCs, one using the traditional switched-capacitor (SC) MDAC and the other using the proposed MDAC, are designed. Simulation results show that the performance of the ADC with the proposed MDAC is enhanced since the power needed for the current sources is smaller than the power supplied by the reference voltage sources. Moreover, the proposed circuit does not require any reference voltage buffer, which can be difficult to design with relatively low power dissipation",

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Goes, JCDP , Paulino, NFSV & DEE Group Author 2011, Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting. in Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES). pp. 216-220, Mixed Design of Integrated Circuits and Systems (MIXDES), 2011, 1/01/11. <http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-80053305005&md5=472e2636d1a1d457e90a15322430ade1>

Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting. / Goes, João Carlos da Palma ; Paulino, Nuno Filipe Silva Veríssimo; DEE Group Author.
Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES). 2011. p. 216-220.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of a 10-bit 40 MS/s pipelined ADC using 1.5-bit with current-mode reference shifting

AU - Goes, João Carlos da Palma

AU - Paulino, Nuno Filipe Silva Veríssimo

AU - DEE Group Author

PY - 2011/1/1

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N2 - This paper presents a 1.5-bit MDAC circuit to be used in pipeline ADCs which employs a switched-current source to perform the reference shifting of the MDAC (the 1.5-bit digital-to-analog function). In the proposed circuit, the two single-ended reference voltage sources that are traditionally used (VREFP and VREFN), are replaced by a switched-current source. To evaluate and compare the performance of the proposed circuit, two 10-bit 40 MS/s ADCs, one using the traditional switched-capacitor (SC) MDAC and the other using the proposed MDAC, are designed. Simulation results show that the performance of the ADC with the proposed MDAC is enhanced since the power needed for the current sources is smaller than the power supplied by the reference voltage sources. Moreover, the proposed circuit does not require any reference voltage buffer, which can be difficult to design with relatively low power dissipation

AB - This paper presents a 1.5-bit MDAC circuit to be used in pipeline ADCs which employs a switched-current source to perform the reference shifting of the MDAC (the 1.5-bit digital-to-analog function). In the proposed circuit, the two single-ended reference voltage sources that are traditionally used (VREFP and VREFN), are replaced by a switched-current source. To evaluate and compare the performance of the proposed circuit, two 10-bit 40 MS/s ADCs, one using the traditional switched-capacitor (SC) MDAC and the other using the proposed MDAC, are designed. Simulation results show that the performance of the ADC with the proposed MDAC is enhanced since the power needed for the current sources is smaller than the power supplied by the reference voltage sources. Moreover, the proposed circuit does not require any reference voltage buffer, which can be difficult to design with relatively low power dissipation

M3 - Conference contribution

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BT - Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)

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