This paper presents a novel method for designing and optimizing high-speed low-voltage two-stage amplifiers with enhanced performance. On the one hand, at circuit level, an additional degree-of-freedom is added to the topology that allows reaching, simultaneously, high DC gain and fast settling response without increasing the power dissipation. On the other hand, an efficient method for optimizing the settling-response of the amplifiers in the time-domain is presented A design example with simulated results is finally shown to validate the proposed ideas.
|Journal||PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I|
|Publication status||Published - 1 Jan 2003|
Santos-tavares, R. M. L., Steiger-garção, A. S., Goes, J. C. D. P., & DEE Group Author (2003). Design and optimization of low-voltage two-stage CMOS amplifiers with enhanced performance. PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, I(NA), 197-200. https://doi.org/10.1109/ISCAS.2003.1205534