TY - GEN
T1 - Depletion Based Digital and Analogue Circuits with n-Channel IGZO Thin Film Transistors
AU - Carvalho, Guilherme
AU - Pereira, Maria
AU - Kiazadeh, Asal
AU - Tavares, Vítor Grade
N1 - info:eu-repo/grantAgreement/FCT/3599-PPCDT/PTDC%2FNAN-MAT%2F30812%2F2017/PT#
info:eu-repo/grantAgreement/FCT/3599-PPCDT/2022.08132.PTDC/PT#
info:eu-repo/grantAgreement/FCT/OE/SFRH%2FBD%2F144376%2F2019/PT#
info:eu-repo/grantAgreement/FCT/CEEC IND4ed/2021.03386.CEECIND%2FCP1657%2FCT0002/PT#
Funding Information:
ACKNOWLEDGMENT This research was funded by FEDER funds through the COMPETE 2020 Programme and National Funds through FCT—Portuguese Foundation for Science and Technology under the Ph.D. grant DFA/BD/8335/2020 of the Associate Laboratory Institute of Nanostructures, Nanomodelling and Nanofabrication – i3N.
Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - In this work, both analogue and digital depletion-mode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with VTH = -0.87V. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity-gain frequency of 444 kHz and a phase margin of 71 degrees.
AB - In this work, both analogue and digital depletion-mode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with VTH = -0.87V. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity-gain frequency of 444 kHz and a phase margin of 71 degrees.
KW - analogue circuits
KW - depletion
KW - digital circuits
KW - Thin film transistors
UR - http://www.scopus.com/inward/record.url?scp=85167704713&partnerID=8YFLogxK
U2 - 10.1109/ISCAS46773.2023.10181633
DO - 10.1109/ISCAS46773.2023.10181633
M3 - Conference contribution
AN - SCOPUS:85167704713
T3 - IEEE International Symposium on Circuits and Systems (ISCAS)
BT - ISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems
PB - Institute of Electrical and Electronics Engineers (IEEE)
CY - New Jersey
T2 - 56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Y2 - 21 May 2023 through 25 May 2023
ER -