Depletion Based Digital and Analogue Circuits with n-Channel IGZO Thin Film Transistors

Guilherme Carvalho, Maria Pereira, Asal Kiazadeh, Vítor Grade Tavares

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Citation (Scopus)

Abstract

In this work, both analogue and digital depletion-mode single channel transistor circuits are presented and are simulated using an n-channel IGZO technology with VTH = -0.87V. A logic family is introduced, suppressing the need for an additional voltage level and level restoring circuitry. Furthermore, in the analogue domain, a depletion current mirror topology is presented with demonstrated small current error. Finally, the current mirror is used in the design of an OpAmp, achieving a simulated open-loop gain of 45 dB, CMRR of 58 dB, unity-gain frequency of 444 kHz and a phase margin of 71 degrees.
Original languageEnglish
Title of host publicationISCAS 2023 - 56th IEEE International Symposium on Circuits and Systems
Place of PublicationNew Jersey
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages5
ISBN (Electronic) 978-1-6654-5109-3
DOIs
Publication statusPublished - 2023
Event56th IEEE International Symposium on Circuits and Systems, ISCAS 2023 - Monterey, United States
Duration: 21 May 202325 May 2023

Publication series

NameIEEE International Symposium on Circuits and Systems (ISCAS)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Volume2023-May
ISSN (Print)0271-4310

Conference

Conference56th IEEE International Symposium on Circuits and Systems, ISCAS 2023
Country/TerritoryUnited States
CityMonterey
Period21/05/2325/05/23

Keywords

  • analogue circuits
  • depletion
  • digital circuits
  • Thin film transistors

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