Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool

P. Sniatala, M. Naumowicz, A. Handkiewicz, S. Szczesny, João L A De Melo, Nuno Filipe Silva Veríssimo Paulino, João Carlos da Palma Goes

Research output: Contribution to journalArticle

14 Citations (Scopus)
106 Downloads (Pure)

Abstract

The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 mu W, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.
Original languageEnglish
Pages (from-to)919–922
Journal Bulletin of the Polish Academy of Sciences Technical Sciences
Volume63
Issue number4
DOIs
Publication statusPublished - 2015

Keywords

  • CAE
  • Current comparator
  • Sigma-delta

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