The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 mu W, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.
|Journal||Bulletin of the Polish Academy of Sciences Technical Sciences|
|Publication status||Published - 2015|
- Current comparator
Sniatala, P., Naumowicz, M., Handkiewicz, A., Szczesny, S., De Melo, J. L. A., Paulino, N. F. S. V., & Goes, J. C. D. P. (2015). Current mode sigma-delta modulator designed with the help of transistor’s size optimization tool. Bulletin of the Polish Academy of Sciences Technical Sciences, 63(4), 919–922. https://doi.org/10.1515/bpasts-2015-0104