Continuous-Time Delta-Sigma Modulators Based on Passive RC Integrators

Joao L.A. de Melo, Nuno Paulino, Joao Goes

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators (ΔΣMs) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the ΔΣM loop filter. A third-order CT ΔΣM is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS Δ ΣM occupies only 0.013 mm², dissipates 256 μW from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a FoMSchreier of 175.1 dB.

Original languageEnglish
Pages (from-to)3662-3674
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume65
Issue number11
DOIs
Publication statusPublished - Nov 2018
Event1st International Symposium on Integrated Circuits and Systems (ISICAS) - Taormina, Italy
Duration: 2 Sep 20183 Sep 2018

Keywords

  • ADC
  • Bandwidth
  • Circuit stability
  • Delta-sigma
  • design
  • Gain
  • Genetic algorithms
  • IoT
  • Mathematical model
  • Modulation
  • optimization
  • passive RC
  • Time-frequency analysis

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