TY - GEN
T1 - Automatic Flat-Level Circuit Generation with Genetic Algorithms
AU - Campilho-Gomes, Miguel
AU - Tavares, Rui
AU - Goes, João
N1 - This work was partially supported by the Fundação para a Ciência e Tecnologia, UIDB/00066/2020 (CTS – Center of Technology and Systems).
PY - 2020
Y1 - 2020
N2 - This paper describes a novel methodology to generate analog and digital circuits, autonomously, using the transistor (or other elementary device, e.g. resistor) as the basic elementary block – flat-level. A genetic algorithm is employed as the generation engine and variable length chromosomes are used to describe the circuit topology that evolves during the search. The circuit devices type and sizing are described by each gene of genetic algorithm. The automatic process starts with the circuit input and output specifications, and proceeds with the circuit topology and sizing evolution to meet those specifications, eventually, ending up with a novel topology. During the evolution, each generated circuit is electrically evaluated by a spice-like circuit simulator, i.e. Ngspice, using full model specifications - like BSIM3 for transistors - in a highly parallelized architecture built over a multi-thread model.
AB - This paper describes a novel methodology to generate analog and digital circuits, autonomously, using the transistor (or other elementary device, e.g. resistor) as the basic elementary block – flat-level. A genetic algorithm is employed as the generation engine and variable length chromosomes are used to describe the circuit topology that evolves during the search. The circuit devices type and sizing are described by each gene of genetic algorithm. The automatic process starts with the circuit input and output specifications, and proceeds with the circuit topology and sizing evolution to meet those specifications, eventually, ending up with a novel topology. During the evolution, each generated circuit is electrically evaluated by a spice-like circuit simulator, i.e. Ngspice, using full model specifications - like BSIM3 for transistors - in a highly parallelized architecture built over a multi-thread model.
KW - Amplifier
KW - Analog circuit
KW - Automatic topology generation
KW - Digital circuit
KW - Genetic algorithm
KW - Ngspice
KW - Variable Length Chromosome
UR - http://www.scopus.com/inward/record.url?scp=85084852440&partnerID=8YFLogxK
U2 - 10.1007/978-3-030-45124-0_9
DO - 10.1007/978-3-030-45124-0_9
M3 - Conference contribution
AN - SCOPUS:85084852440
SN - 978-3-030-45123-3
T3 - IFIP Advances in Information and Communication Technology
SP - 101
EP - 108
BT - Technological Innovation for Life Improvement - 11th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2020, Proceedings
A2 - Camarinha-Matos, Luis M.
A2 - Farhadi, Nastaran
A2 - Lopes, Fábio
A2 - Pereira, Helena
PB - Springer
CY - Cham
T2 - 11th Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2020
Y2 - 1 July 2020 through 3 July 2020
ER -