Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model

Rodrigo D. Pinto; Pedro Toledo; João P. Oliveira

doi:10.1109/YEF-ECE58420.2023.10209294

Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model

Rodrigo D. Pinto, Pedro Toledo, João P. Oliveira

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper uses a design-oriented 7-parameter MOSFET model to assess the Zero Distortion Bias Point (ZDBP). The ZDBP existence and its dependencies on the main Short-Channel Effects (SCE) typically found in advanced CMOS technologies such as Drain-Induced Barrier Lowering (DIBL), carrier velocity saturation, carrier mobility reduction, and Channel Length Modulation (CLM) are herein investigated. The design-oriented model used here is based on the inversion charge concept which preserves the physics of the MOS transistor, while keeping valid for all bias regimes (from weak to strong inversion) and all operating regions (linear and saturated). Across technologies, this paper's results demonstrate that ZDBP appears around the Threshold Voltage (VTH) when carrier mobility reduction and carrier velocity saturation are included in the model and its localization orbits around the VTH-55mV < VTH < VTH + 100mV depending mainly on the DIBL and carrier mobility reduction parameters.

Original language	English
Title of host publication	Proceedings
Subtitle of host publication	2023 International Young Engineers Forum in Electrical and Computer Engineering, YEF-ECE 2023
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	84-88
Number of pages	5
ISBN (Electronic)	979-8-3503-0042-0
ISBN (Print)	979-8-3503-0043-7
DOIs	https://doi.org/10.1109/YEF-ECE58420.2023.10209294
Publication status	Published - 2023
Event	2023 International Young Engineers Forum in Electrical and Computer Engineering - Caparica, Lisbon, Portugal Duration: 7 Jul 2023 → 7 Jul 2023

Conference

Conference	2023 International Young Engineers Forum in Electrical and Computer Engineering
Abbreviated title	YEF-ECE 2023
Country/Territory	Portugal
City	Lisbon
Period	7/07/23 → 7/07/23

Keywords

Harmonic Distortion
MOS Transistor
Short-Channel Effects (SCE)
Zero Distortion Bias Point (ZDBP)

Access to Document

10.1109/YEF-ECE58420.2023.10209294

Cite this

Pinto, R. D., Toledo, P., & Oliveira, J. P. (2023). Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model. In Proceedings: 2023 International Young Engineers Forum in Electrical and Computer Engineering, YEF-ECE 2023 (pp. 84-88). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/YEF-ECE58420.2023.10209294

@inproceedings{7e28fded384844fc9d123d573d8e90d4,

title = "Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model",

abstract = "This paper uses a design-oriented 7-parameter MOSFET model to assess the Zero Distortion Bias Point (ZDBP). The ZDBP existence and its dependencies on the main Short-Channel Effects (SCE) typically found in advanced CMOS technologies such as Drain-Induced Barrier Lowering (DIBL), carrier velocity saturation, carrier mobility reduction, and Channel Length Modulation (CLM) are herein investigated. The design-oriented model used here is based on the inversion charge concept which preserves the physics of the MOS transistor, while keeping valid for all bias regimes (from weak to strong inversion) and all operating regions (linear and saturated). Across technologies, this paper's results demonstrate that ZDBP appears around the Threshold Voltage (VTH) when carrier mobility reduction and carrier velocity saturation are included in the model and its localization orbits around the VTH-55mV < VTH < VTH + 100mV depending mainly on the DIBL and carrier mobility reduction parameters.",

keywords = "Harmonic Distortion, MOS Transistor, Short-Channel Effects (SCE), Zero Distortion Bias Point (ZDBP)",

author = "Pinto, {Rodrigo D.} and Pedro Toledo and Oliveira, {Jo{\~a}o P.}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International Young Engineers Forum in Electrical and Computer Engineering<br/>, YEF-ECE 2023 ; Conference date: 07-07-2023 Through 07-07-2023",

year = "2023",

doi = "10.1109/YEF-ECE58420.2023.10209294",

language = "English",

isbn = "979-8-3503-0043-7",

pages = "84--88",

booktitle = "Proceedings",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Pinto, RD, Toledo, P & Oliveira, JP 2023, Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model. in Proceedings: 2023 International Young Engineers Forum in Electrical and Computer Engineering, YEF-ECE 2023. Institute of Electrical and Electronics Engineers (IEEE), pp. 84-88, 2023 International Young Engineers Forum in Electrical and Computer Engineering
, Lisbon, Portugal, 7/07/23. https://doi.org/10.1109/YEF-ECE58420.2023.10209294

Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model. / Pinto, Rodrigo D.; Toledo, Pedro; Oliveira, João P.
Proceedings: 2023 International Young Engineers Forum in Electrical and Computer Engineering, YEF-ECE 2023. Institute of Electrical and Electronics Engineers (IEEE), 2023. p. 84-88.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model

AU - Pinto, Rodrigo D.

AU - Toledo, Pedro

AU - Oliveira, João P.

PY - 2023

Y1 - 2023

N2 - This paper uses a design-oriented 7-parameter MOSFET model to assess the Zero Distortion Bias Point (ZDBP). The ZDBP existence and its dependencies on the main Short-Channel Effects (SCE) typically found in advanced CMOS technologies such as Drain-Induced Barrier Lowering (DIBL), carrier velocity saturation, carrier mobility reduction, and Channel Length Modulation (CLM) are herein investigated. The design-oriented model used here is based on the inversion charge concept which preserves the physics of the MOS transistor, while keeping valid for all bias regimes (from weak to strong inversion) and all operating regions (linear and saturated). Across technologies, this paper's results demonstrate that ZDBP appears around the Threshold Voltage (VTH) when carrier mobility reduction and carrier velocity saturation are included in the model and its localization orbits around the VTH-55mV < VTH < VTH + 100mV depending mainly on the DIBL and carrier mobility reduction parameters.

AB - This paper uses a design-oriented 7-parameter MOSFET model to assess the Zero Distortion Bias Point (ZDBP). The ZDBP existence and its dependencies on the main Short-Channel Effects (SCE) typically found in advanced CMOS technologies such as Drain-Induced Barrier Lowering (DIBL), carrier velocity saturation, carrier mobility reduction, and Channel Length Modulation (CLM) are herein investigated. The design-oriented model used here is based on the inversion charge concept which preserves the physics of the MOS transistor, while keeping valid for all bias regimes (from weak to strong inversion) and all operating regions (linear and saturated). Across technologies, this paper's results demonstrate that ZDBP appears around the Threshold Voltage (VTH) when carrier mobility reduction and carrier velocity saturation are included in the model and its localization orbits around the VTH-55mV < VTH < VTH + 100mV depending mainly on the DIBL and carrier mobility reduction parameters.

KW - Harmonic Distortion

KW - MOS Transistor

KW - Short-Channel Effects (SCE)

KW - Zero Distortion Bias Point (ZDBP)

UR - http://www.scopus.com/inward/record.url?scp=85168887835&partnerID=8YFLogxK

U2 - 10.1109/YEF-ECE58420.2023.10209294

DO - 10.1109/YEF-ECE58420.2023.10209294

M3 - Conference contribution

AN - SCOPUS:85168887835

SN - 979-8-3503-0043-7

SP - 84

EP - 88

BT - Proceedings

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 2023 International Young Engineers Forum in Electrical and Computer Engineering<br/>

Y2 - 7 July 2023 through 7 July 2023

ER -

Assessment of the Zero Distortion Bias Point Using Design-Oriented 7-Parameter MOSFET Model

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this