Analysis and the design of a first - Order ΔΣ modulator using very incomplete settling

João Carlos da Palma Goes; Nuno Filipe Silva Veríssimo Paulino

Analysis and the design of a first - Order ΔΣ modulator using very incomplete settling

João Carlos da Palma Goes, Nuno Filipe Silva Veríssimo Paulino

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

One of the main building blocks of a Delta-Sigma modulator (ΔΣM) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣ circuit based on the implementation of passive switched-capacitor (SC) integrator using very incomplete settling. The behavior of a 1storder ΔΣM is fully analyzed and explained. Electrical simulations show that the ΔΣM achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 62 dB, a peak signal-to-noise ratio (SNR) of 63 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating only 130 μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 213 fJ/conv.-step (simulated).

Original language	Unknown
Title of host publication	Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011
Pages	274-278
Publication status	Published - 1 Jan 2011
Event	Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 - Duration: 1 Jan 2011 → …

Conference

Conference	Mixed Design of Integrated Circuits and Systems (MIXDES), 2011
Period	1/01/11 → …

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Cite this

Goes, J. C. D. P., & Paulino, N. F. S. V. (2011). Analysis and the design of a first - Order ΔΣ modulator using very incomplete settling. In Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 (pp. 274-278) http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-80053313045&md5=ddfbcd4e7ce5d7c5345f441316d4061d

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abstract = "One of the main building blocks of a Delta-Sigma modulator (ΔΣM) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣ circuit based on the implementation of passive switched-capacitor (SC) integrator using very incomplete settling. The behavior of a 1storder ΔΣM is fully analyzed and explained. Electrical simulations show that the ΔΣM achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 62 dB, a peak signal-to-noise ratio (SNR) of 63 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating only 130 μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 213 fJ/conv.-step (simulated).",

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Goes, JCDP & Paulino, NFSV 2011, Analysis and the design of a first - Order ΔΣ modulator using very incomplete settling. in Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011. pp. 274-278, Mixed Design of Integrated Circuits and Systems (MIXDES), 2011, 1/01/11. <http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-80053313045&md5=ddfbcd4e7ce5d7c5345f441316d4061d>

Analysis and the design of a first - Order ΔΣ modulator using very incomplete settling. / Goes, João Carlos da Palma ; Paulino, Nuno Filipe Silva Veríssimo.
Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011. 2011. p. 274-278.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Analysis and the design of a first - Order ΔΣ modulator using very incomplete settling

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N2 - One of the main building blocks of a Delta-Sigma modulator (ΔΣM) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣ circuit based on the implementation of passive switched-capacitor (SC) integrator using very incomplete settling. The behavior of a 1storder ΔΣM is fully analyzed and explained. Electrical simulations show that the ΔΣM achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 62 dB, a peak signal-to-noise ratio (SNR) of 63 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating only 130 μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 213 fJ/conv.-step (simulated).

AB - One of the main building blocks of a Delta-Sigma modulator (ΔΣM) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣ circuit based on the implementation of passive switched-capacitor (SC) integrator using very incomplete settling. The behavior of a 1storder ΔΣM is fully analyzed and explained. Electrical simulations show that the ΔΣM achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 62 dB, a peak signal-to-noise ratio (SNR) of 63 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating only 130 μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 213 fJ/conv.-step (simulated).

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BT - Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2011

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