This paper presents a new technique for the design of receiver architectures, based on the use of variable reference voltages in ADCs. The main goal is to improve the SNDR of a receiver chain when compared to traditional architectures like Low-IF or Subsampling, while performing down-conversion without the need of a Mixer block. The proposed technique takes advantage of the inherent capability of the ADC to perform the multiplication operation. High-level model simulations show that this technique is capable of improving the SNDR by about 5 dB (from 50 to 55 dB), while avoiding out-of-band noise aliasing, when compared to the referred techniques.
|Title of host publication||Circuits and Systems (ISCAS), 2014 IEEE International Symposium on|
|Publication status||Published - 2014|
|Event||IEEE Int. Symp. Circuits and Systems (ISCAS’14) - |
Duration: 1 Jan 2014 → …
|Conference||IEEE Int. Symp. Circuits and Systems (ISCAS’14)|
|Period||1/01/14 → …|