An Improved Low-Voltage Low-Power CMOS Comparator to be used in High-Speed Pipeline ADCs

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26 Citations (Scopus)

Abstract

This paper presents an improved low-voltage low-power CMOS comparator suitable for high-speed pipeline ADCs. Simulated results of the proposed circuit in a 0.35 μm standard CMOS technology operating at supply voltages within the range of 1.0-1.5 V show that this comparator achieves low offset, reduced kickback noise, high mean-time to failure and exhibits low-power dissipation at very high-speed operation.
Original languageEnglish
Title of host publication-
Pagespp. V-141- V-144
Number of pages4
Volume5
DOIs
Publication statusPublished - 1 Jan 2002
EventIEEE International Symposium on Circuits and Systems ISCAS 2002 -
Duration: 1 Jan 2002 → …

Conference

ConferenceIEEE International Symposium on Circuits and Systems ISCAS 2002
Period1/01/02 → …

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