TY - JOUR
T1 - An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification.
AU - Goes, João Carlos da Palma
AU - Oliveira, João Pedro Abreu de
AU - DEE Group Author
PY - 2010/1/1
Y1 - 2010/1/1
N2 - This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, −47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noiseplus- distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.
AB - This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, −47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noiseplus- distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.
U2 - 10.1109/TCSII.2009.2038632
DO - 10.1109/TCSII.2009.2038632
M3 - Article
SN - 1549-7747
VL - 57
SP - 105
EP - 109
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 2
ER -