An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification.

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Abstract

This brief presents an 8-bit 120-MS/s time-interleaved pipeline analog-to-digital converter (ADC) fully based on MOS discrete-time parametric amplification. The ADC, fabricated in a 130-nm CMOS logic process, features an active area below 0.12mm2, where only MOS devices are used. Measurement results for a 20-MHz input signal shows that the ADC achieves 39.7 dB of signal-to-noise ratio, 49.3 dB of spurious-free dynamic range, −47.5 dB of total harmonic distortion, 39.1 dB of signal-to-noiseplus- distortion ratio, and 6.2 bits of peak effective number of bits while consuming less than 14 mW from a 1.2-V supply.
Original languageUnknown
Pages (from-to)105-109
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume57
Issue number2
DOIs
Publication statusPublished - 1 Jan 2010

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