TY - JOUR
T1 - All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications
AU - Correia, Ana
AU - Tavares, Vítor Grade
AU - Barquinha, Pedro
AU - Goes, João
N1 - Funding Information:
info:eu-repo/grantAgreement/FCT/OE/SFRH%2FBD%2F137519%2F2018/PT#
info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDB%2F50025%2F2020/PT#
SMART-E-PTDC/CTM-PAM/04012/2022, IDS-PAPER-PTDC/CTM-PAM/4241/2020 and PEST (CTS/UNINOVA)-UIDB/00066/2020. This work also received funding from the European Community’s H2020 program [Grant Agreement No. 716510 (ERC-2016-StG TREND) and 952169 (SYNERGY, H2020-WIDESPREAD-2020-5, CSA)].
Publisher Copyright:
© 2022 by the authors.
PY - 2022/12/7
Y1 - 2022/12/7
N2 - In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated (Formula presented.) is close to 16.2 fJ/conv.-step.
AB - In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated (Formula presented.) is close to 16.2 fJ/conv.-step.
KW - all-standard-cell-based
KW - analog-to-digital converters
KW - digital–delta modulator ADC
KW - high resolution
KW - Internet of Things
KW - noise shaping
UR - http://www.scopus.com/inward/record.url?scp=85144668204&partnerID=8YFLogxK
U2 - 10.3390/jlpea12040064
DO - 10.3390/jlpea12040064
M3 - Article
AN - SCOPUS:85144668204
VL - 12
JO - Journal of Low Power Electronics and Applications
JF - Journal of Low Power Electronics and Applications
IS - 4
M1 - 64
ER -
