this paper introduces a tool for the optimization of CMOS integrated spiral inductors. Its aim is to offer designers a first approach on designing inductors without the need for fabrication. The core of the tool is an optimization procedure where technology constraints on the inductor layout parameters are considered by applying user-defined discretization on the design variables. User-defined constraints between layout parameters may also be accounted for, as a way of taking into account design heuristics. For those cases where the device area is a major concern area minimization may be considered. On the other hand, if a major design goal is the inductor quality factor the tool may yield the layout parameters which maximize the quality factor. The trade-off between quality factor and device area is evaluated through the generation of a graphical representation of quality factor versus output diameter for a given inductance. For the sake of simplicity the 蟺-model has been used for characterising the inductor. The application was developed in Matlab and the optimization toolbox is used. The validity of the design results obtained is checked against circuit simulation with ASITIC.
|Title of host publication||-|
|Publication status||Published - 1 Jan 2009|
|Event||IEEE The 16th IEEE International Conference on Electronics, Circuits, and Systems - |
Duration: 1 Jan 2009 → …
|Conference||IEEE The 16th IEEE International Conference on Electronics, Circuits, and Systems|
|Period||1/01/09 → …|