A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC

Nuno Pereira; Hugo Serra; Joao Goes

doi:10.1109/ISCAS.2017.8050563

A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC

Nuno Pereira, Hugo Serra, Joao Goes

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Citations (Scopus)

Abstract

In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050563
Publication status	Published - 25 Sept 2017
Event	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: 28 May 2017 → 31 May 2017

Conference

Conference	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/Territory	United States
City	Baltimore
Period	28/05/17 → 31/05/17

Keywords

analog-to-digital converters
charge-sharing
embedded mixing
receivers
successive-approximations

Access to Document

10.1109/ISCAS.2017.8050563Licence: Unspecified

Cite this

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title = "A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC",

abstract = "In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.",

keywords = "analog-to-digital converters, charge-sharing, embedded mixing, receivers, successive-approximations",

author = "Nuno Pereira and Hugo Serra and Joao Goes",

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Pereira, N , Serra, H & Goes, J 2017, A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050563, Institute of Electrical and Electronics Engineers (IEEE), 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 28/05/17. https://doi.org/10.1109/ISCAS.2017.8050563

A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. / Pereira, Nuno ; Serra, Hugo ; Goes, Joao.
IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers (IEEE), 2017. 8050563.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC

AU - Pereira, Nuno

AU - Serra, Hugo

AU - Goes, Joao

N1 - Sem PDF. national funds through FCT - Fundacao para a Ciencia e Tecnologia (PEst-OE/EEI/UI0066/2013; SFRH/BD/94933/2013; SFRH/BD/87476/2012) PROTEUS of the European Union's H Programme for research, technological development and demonstration (644852)

PY - 2017/9/25

Y1 - 2017/9/25

N2 - In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

AB - In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

KW - analog-to-digital converters

KW - charge-sharing

KW - embedded mixing

KW - receivers

KW - successive-approximations

UR - https://www.scopus.com/pages/publications/85032677263

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DO - 10.1109/ISCAS.2017.8050563

M3 - Conference contribution

AN - SCOPUS:85032677263

BT - IEEE International Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017

Y2 - 28 May 2017 through 31 May 2017

ER -

A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC

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Keywords

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