A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
Publication statusPublished - 25 Sep 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 28 May 201731 May 2017

Conference

Conference50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period28/05/1731/05/17

Fingerprint

Radio receivers
FIR filters
Sampling
Networks (circuits)

Keywords

  • analog-to-digital converters
  • charge-sharing
  • embedded mixing
  • receivers
  • successive-approximations

Cite this

Pereira, N., Serra, H., & Goes, J. (2017). A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050563] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050563
Pereira, Nuno ; Serra, Hugo ; Goes, Joao. / A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017.
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abstract = "In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.",
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Pereira, N, Serra, H & Goes, J 2017, A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050563, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 28/05/17. https://doi.org/10.1109/ISCAS.2017.8050563

A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. / Pereira, Nuno; Serra, Hugo; Goes, Joao.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050563.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

AB - In this work, a new two-step radio receiver architecture is proposed, fully embedding two downconversion stages into a charge-sharing (CS) SAR ADC. In order to relax the sampling rate requirements of the ADC, the input signal is firstly downconverted into a specific IF prior to quantization, by a 4-Tap time-interleaved FIR filter in a subsampling manner. Since the ADC can embed the downconversion operation, a smaller subsampling ratio can be used, thus reducing the out-of-band noise density at the output and improving performance. Circuit-level simulations demonstrate, through an 8-bit CS SAR ADC, a SNDR of 48.2 dB, THD of -56.6 dB and a SFDR of 55.1 dB, in a structure that entirely renounce conventional mixer stages. As a consequence, significant power and area savings are expected, together with improved noise and linearity performances.

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Pereira N, Serra H, Goes J. A two-step radio receiver architecture fully embedded into a charge-sharing SAR ADC. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050563 https://doi.org/10.1109/ISCAS.2017.8050563