TY - JOUR
T1 - A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency
AU - Santos-tavares, Rui Manuel Leitão
AU - Goes, João Carlos da Palma
AU - DEE Group Author
PY - 2011/1/1
Y1 - 2011/1/1
N2 - A two-stage fully differential CMOS amplifier comprising inverters as input devices and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy-efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasiclass- A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, and slew rate are carried out. Based on these analyses, a manual design methodology and genetic algorithm based optimization is presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13μm 1.2 V standard CMOS technology are shown.
AB - A two-stage fully differential CMOS amplifier comprising inverters as input devices and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy-efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasiclass- A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, and slew rate are carried out. Based on these analyses, a manual design methodology and genetic algorithm based optimization is presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13μm 1.2 V standard CMOS technology are shown.
KW - fully differential
KW - self-biased
KW - inverter
KW - operational transconductance amplifier
KW - Amplifier
KW - CMOS analog integrated circuits
U2 - 10.1109/TCSI.2011.2150910
DO - 10.1109/TCSI.2011.2150910
M3 - Article
SN - 1057-7122
VL - 58
SP - 1591
EP - 1603
JO - Ieee Transactions On Circuits And Systems I-Regular Papers
JF - Ieee Transactions On Circuits And Systems I-Regular Papers
IS - 7(SI)
ER -